soc/amd/common/block/apob/apob_cache: use APOB cache size from FMAP
[coreboot.git] / src / include / base3.h
blob6bcf3356ad13895eb9eb27ea7e68ba8c6234f1fd
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __SRC_INCLUDE_BASE3_H__
4 #define __SRC_INCLUDE_BASE3_H__
6 /* We translate a floating pin (Z) as the ternary digit 2. */
7 #define Z 2
9 /*
10 * This provides a variadic macro BASE3() that can be used to translate a set of
11 * pin states into its base-3 integer representation, even in the context of a
12 * static initializer. You can call it with any number of up to 6 arguments,
13 * e.g. BASE3(1, Z) -> 5 or BASE3(0, Z, 1, 0) -> 21. Just don't look too closely
14 * at how the sausage is made. (Pay extra attention to typos when expanding it!)
16 #define _BASE3_IMPL_1(arg0, arg1, arg2, arg3, arg4, arg5) arg0
17 #define _BASE3_IMPL_2(arg0, arg1, arg2, arg3, arg4, arg5) \
18 (arg1 + (3 * _BASE3_IMPL_1(arg0, arg1, arg2, arg3, arg4, arg5)))
19 #define _BASE3_IMPL_3(arg0, arg1, arg2, arg3, arg4, arg5) \
20 (arg2 + (3 * _BASE3_IMPL_2(arg0, arg1, arg2, arg3, arg4, arg5)))
21 #define _BASE3_IMPL_4(arg0, arg1, arg2, arg3, arg4, arg5) \
22 (arg3 + (3 * _BASE3_IMPL_3(arg0, arg1, arg2, arg3, arg4, arg5)))
23 #define _BASE3_IMPL_5(arg0, arg1, arg2, arg3, arg4, arg5) \
24 (arg4 + (3 * _BASE3_IMPL_4(arg0, arg1, arg2, arg3, arg4, arg5)))
25 #define _BASE3_IMPL_6(arg0, arg1, arg2, arg3, arg4, arg5) \
26 (arg5 + (3 * _BASE3_IMPL_5(arg0, arg1, arg2, arg3, arg4, arg5)))
27 #define _BASE3_IMPL(arg0, arg1, arg2, arg3, arg4, arg5, NARGS, ...) \
28 _BASE3_IMPL##NARGS(arg0, arg1, arg2, arg3, arg4, arg5)
29 #define BASE3(...) _BASE3_IMPL(__VA_ARGS__, _6, _5, _4, _3, _2, _1)
31 #endif /* __SRC_INCLUDE_BASE3_H__ */