2 * This file is part of the coreboot project.
4 * Copyright (C) 2013 Google Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <device/pci_ops.h>
18 #include <soc/iomap.h>
20 #include <soc/pci_devs.h>
21 #include <soc/romstage.h>
23 void byt_config_com1_and_enable(void)
27 /* Enable the UART hardware for COM1. */
29 pci_write_config32(PCI_DEV(0, LPC_DEV
, 0), UART_CONT
, reg
);
31 /* Set up the pads to select the UART function */
32 score_select_func(UART_RXD_PAD
, 1);
33 score_select_func(UART_TXD_PAD
, 1);