2 # This file is part of the coreboot project.
4 # Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
6 # This program is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; version 2 of the License.
10 # This program is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 # GNU General Public License for more details.
15 # You should have received a copy of the GNU General Public License
16 # along with this program; if not, write to the Free Software
17 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 default y if CPU_AMD_AGESA_FAMILY10
23 default y if CPU_AMD_AGESA_FAMILY12
24 default y if CPU_AMD_AGESA_FAMILY14
25 default y if CPU_AMD_AGESA_FAMILY15
26 default y if CPU_AMD_AGESA_FAMILY15_TN
28 select TSC_SYNC_LFENCE
30 select LAPIC_MONOTONIC_TIMER
42 Overwride the default write through caching size as 1M Bytes.
43 On some AMD paltform, one socket support 2 or more kinds of
44 processor family, compiling several cpu families agesa code
45 will increase the romstage size.
46 In order to execute romstage in place on the flash rom,
47 more space is required to be set as write through caching.
49 config UDELAY_LAPIC_FIXED_FSB
53 source src/cpu/amd/agesa/family10/Kconfig
54 source src/cpu/amd/agesa/family12/Kconfig
55 source src/cpu/amd/agesa/family14/Kconfig
56 source src/cpu/amd/agesa/family15/Kconfig
57 source src/cpu/amd/agesa/family15tn/Kconfig