src/mainboard/jetway/nf81-t56n-lf/buildOpts.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /**
   4  * @file
   5  *
   6  * AMD User options selection for a Brazos platform solution system
   7  *
   8  * This file is placed in the user's platform directory and contains the
   9  * build option selections desired for that platform.
  10  *
  11  * For Information about this file, see @ref platforminstall.
  12  */
  13
  14 #include <vendorcode/amd/agesa/f14/AGESA.h>
  15
  16 /* Include the files that instantiate the configuration definitions. */
  17 #include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h>
  18 #include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h>
  19 #include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h>
  20 #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
  21 /* AGESA nonesense: the next two headers depend on heapManager.h */
  22 #include <vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h>
  23 #include <vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h>
  24 /* These tables are optional and may be used to adjust memory timing settings */
  25 #include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h>
  26 #include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h>
  27
  28 /* Select the CPU family. */
  29 #define INSTALL_FAMILY_14_SUPPORT TRUE
  30
  31 /* Select the CPU socket type. */
  32 #define INSTALL_FT1_SOCKET_SUPPORT      TRUE
  33
  34 /**
  35  * AGESA optional capabilities selection.
  36  * Uncomment and mark FALSE those features you wish to include in the build.
  37  * Comment out or mark TRUE those features you want to REMOVE from the build.
  38  */
  39
  40 #define BLDOPT_REMOVE_UDIMMS_SUPPORT                    FALSE
  41 #define BLDOPT_REMOVE_RDIMMS_SUPPORT                    TRUE
  42 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT                   FALSE
  43 #define BLDOPT_REMOVE_ECC_SUPPORT                               FALSE
  44 //#define BLDOPT_REMOVE_DCT_INTERLEAVE                  TRUE
  45 #define BLDOPT_REMOVE_BANK_INTERLEAVE                   FALSE
  46 #define BLDOPT_REMOVE_NODE_INTERLEAVE                   TRUE
  47 #define BLDOPT_REMOVE_PARALLEL_TRAINING                 FALSE
  48 #define BLDOPT_REMOVE_DQS_TRAINING                              FALSE
  49 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT              TRUE
  50 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT               TRUE
  51                 #define BLDOPT_REMOVE_ACPI_PSTATES                              FALSE
  52                 #define BLDCFG_REMOVE_ACPI_PSTATES_PPC                  FALSE
  53                 #define BLDCFG_REMOVE_ACPI_PSTATES_PCT                  FALSE
  54                 #define BLDCFG_REMOVE_ACPI_PSTATES_PSD                  FALSE
  55                 #define BLDCFG_REMOVE_ACPI_PSTATES_PSS                  FALSE
  56                 #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS                 FALSE
  57                 #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT             FALSE
  58 #define BLDOPT_REMOVE_SRAT                                              FALSE
  59 #define BLDOPT_REMOVE_SLIT                                              FALSE
  60 #define BLDOPT_REMOVE_WHEA                                              FALSE
  61 #define BLDOPT_REMOVE_DMI                                               TRUE
  62 #define BLDOPT_REMOVE_HT_ASSIST                                 TRUE
  63 #define BLDOPT_REMOVE_ATM_MODE                                  TRUE
  64 //#define BLDOPT_REMOVE_MSG_BASED_C1E                   TRUE
  65 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT     TRUE
  66 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT               FALSE
  67 //#define BLDOPT_REMOVE_C6_STATE                                TRUE
  68 #define BLDOPT_REMOVE_GFX_RECOVERY                              TRUE
  69 #define BLDOPT_REMOVE_EARLY_SAMPLES                             TRUE
  70
  71 #define BLDCFG_VRM_CURRENT_LIMIT                                24000
  72 //#define BLDCFG_VRM_NB_CURRENT_LIMIT                   0
  73 #define BLDCFG_VRM_LOW_POWER_THRESHOLD                  24000
  74 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD               1
  75 #define BLDCFG_VRM_SLEW_RATE                                    5000
  76 //#define BLDCFG_VRM_NB_SLEW_RATE                               5000
  77 //#define BLDCFG_VRM_ADDITIONAL_DELAY                   0
  78 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY                0
  79 #define BLDCFG_VRM_HIGH_SPEED_ENABLE                    TRUE
  80 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE               FALSE
  81 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT                 6000
  82 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT    0
  83
  84 //#define BLDCFG_PROCESSOR_SCOPE_NAME0                  'C'
  85 //#define BLDCFG_PROCESSOR_SCOPE_NAME1                  '0'
  86 //#define BLDCFG_PROCESSOR_SCOPE_IN_SB                  FALSE
  87 #define BLDCFG_PLAT_NUM_IO_APICS                                3
  88 //#define BLDCFG_PLATFORM_C1E_MODE                              C1eModeDisabled
  89 //#define BLDCFG_PLATFORM_C1E_OPDATA                    0
  90 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1              0
  91 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2              0
  92 #define BLDCFG_PLATFORM_CSTATE_MODE                             CStateModeC6
  93 #define BLDCFG_PLATFORM_CSTATE_OPDATA                   0x840
  94 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
  95 //#define BLDCFG_PLATFORM_CPB_MODE                              CpbModeAuto
  96 #define BLDCFG_CORE_LEVELING_MODE                               CORE_LEVEL_LOWEST
  97 #define BLDCFG_AMD_PLATFORM_TYPE                                AMD_PLATFORM_MOBILE
  98 //#define BLDCFG_STARTING_BUSNUM                                0
  99 //#define BLDCFG_MAXIMUM_BUSNUM                                 0xf8
 100 //#define BLDCFG_ALLOCATED_BUSNUMS                              0x20
 101 //#define BLDCFG_PLATFORM_DEEMPHASIS_LIST               0
 102 //#define BLDCFG_BUID_SWAP_LIST                                 0
 103 //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST    0
 104 //#define BLDCFG_HTFABRIC_LIMITS_LIST                   0
 105 //#define BLDCFG_HTCHAIN_LIMITS_LIST                    0
 106 //#define BLDCFG_BUS_NUMBERS_LIST                               0
 107 //#define BLDCFG_IGNORE_LINK_LIST                               0
 108 //#define BLDCFG_LINK_SKIP_REGANG_LIST                  0
 109 //#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST             0
 110 //#define BLDCFG_USE_HT_ASSIST                                  TRUE
 111 //#define BLDCFG_USE_ATM_MODE                                   TRUE
 112 //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE             Nfcm
 113 #define BLDCFG_S3_LATE_RESTORE                                  TRUE
 114 //#define BLDCFG_USE_32_BYTE_REFRESH                    FALSE
 115 //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
 116 //#define BLDCFG_PLATFORM_POWER_POLICY_MODE             Performance
 117 //#define BLDCFG_SET_HTCRC_SYNC_FLOOD                   FALSE
 118 //#define BLDCFG_USE_UNIT_ID_CLUMPING                   FALSE
 119 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP             0
 120 #define BLDCFG_CFG_GNB_HD_AUDIO                                 FALSE
 121 //#define BLDCFG_CFG_ABM_SUPPORT                                FALSE
 122 //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE               0
 123 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL             0
 124 //#define BLDCFG_MEM_INIT_PSTATE                                0
 125 //#define BLDCFG_AMD_PSTATE_CAP_VALUE                   0
 126 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT               DDR1333_FREQUENCY
 127 #define BLDCFG_MEMORY_MODE_UNGANGED                             TRUE
 128 //#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE               TRUE
 129 //#define BLDCFG_MEMORY_QUADRANK_TYPE                   QUADRANK_UNBUFFERED
 130 #define BLDCFG_MEMORY_SODIMM_CAPABLE                    TRUE
 131 #define BLDCFG_MEMORY_LRDIMM_CAPABLE                    FALSE
 132 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING  TRUE
 133 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING  FALSE
 134 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING              FALSE
 135 #define BLDCFG_MEMORY_POWER_DOWN                                TRUE
 136 #define BLDCFG_POWER_DOWN_MODE                                  POWER_DOWN_BY_CHIP_SELECT
 137 //#define BLDCFG_ONLINE_SPARE                                   FALSE
 138 //#define BLDCFG_MEMORY_PARITY_ENABLE                   FALSE
 139 #define BLDCFG_BANK_SWIZZLE                                             TRUE
 140 #define BLDCFG_TIMING_MODE_SELECT                               TIMING_MODE_AUTO
 141 #define BLDCFG_MEMORY_CLOCK_SELECT                              DDR1333_FREQUENCY
 142 #define BLDCFG_DQS_TRAINING_CONTROL                             TRUE
 143 #define BLDCFG_IGNORE_SPD_CHECKSUM                              FALSE
 144 #define BLDCFG_USE_BURST_MODE                                   FALSE
 145 #define BLDCFG_MEMORY_ALL_CLOCKS_ON                             FALSE
 146 //#define BLDCFG_ENABLE_ECC_FEATURE                             TRUE
 147 //#define BLDCFG_ECC_REDIRECTION                                FALSE
 148 //#define BLDCFG_SCRUB_DRAM_RATE                                0
 149 //#define BLDCFG_SCRUB_L2_RATE                                  0
 150 //#define BLDCFG_SCRUB_L3_RATE                                  0
 151 //#define BLDCFG_SCRUB_IC_RATE                                  0
 152 //#define BLDCFG_SCRUB_DC_RATE                                  0
 153 //#define BLDCFG_ECC_SYNC_FLOOD                                 0
 154 //#define BLDCFG_ECC_SYMBOL_SIZE                                0
 155 //#define BLDCFG_1GB_ALIGN                                              FALSE
 156 #define BLDCFG_UMA_ALLOCATION_MODE                              UMA_AUTO
 157 #define BLDCFG_UMA_ALLOCATION_SIZE                              0
 158 #define BLDCFG_UMA_ABOVE4G_SUPPORT                              FALSE
 159 #define BLDCFG_UMA_ALIGNMENT                                    NO_UMA_ALIGNED
 160 #define BLDCFG_HEAP_DRAM_ADDRESS                                0xB0000
 161 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
 162
 163 /**
 164  * AGESA configuration values selection.
 165  * Uncomment and specify the value for the configuration options
 166  * needed by the system.
 167  */
 168
 169 /* MEMORY_BUS_SPEED */
 170 #define DDR400_FREQUENCY                                200 /**< DDR 400 */
 171 #define DDR533_FREQUENCY                                266 /**< DDR 533 */
 172 #define DDR667_FREQUENCY                                333 /**< DDR 667 */
 173 #define DDR800_FREQUENCY                                400 /**< DDR 800 */
 174 #define DDR1066_FREQUENCY                               533 /**< DDR 1066 */
 175 #define DDR1333_FREQUENCY                               667 /**< DDR 1333 */
 176 #define DDR1600_FREQUENCY                               800 /**< DDR 1600 */
 177 #define DDR1866_FREQUENCY                               933 /**< DDR 1866 */
 178 #define UNSUPPORTED_DDR_FREQUENCY               934 /**< Max limit of DDR frequency */
 179
 180 /* QUANDRANK_TYPE */
 181 #define QUADRANK_REGISTERED                             0 /**< Quadrank registered DIMM */
 182 #define QUADRANK_UNBUFFERED                             1 /**< Quadrank unbuffered DIMM */
 183
 184 /* USER_MEMORY_TIMING_MODE */
 185 #define TIMING_MODE_AUTO                                0 /**< Use best rate possible */
 186 #define TIMING_MODE_LIMITED                             1 /**< Set user top limit */
 187 #define TIMING_MODE_SPECIFIC                    2 /**< Set user specified speed */
 188
 189 /* POWER_DOWN_MODE */
 190 #define POWER_DOWN_BY_CHANNEL                   0 /**< Channel power down mode */
 191 #define POWER_DOWN_BY_CHIP_SELECT               1 /**< Chip select power down mode */
 192
 193 /**
 194  * The following definitions specify the default values for various parameters
 195  * in which there are no clearly defined defaults to be used in the common
 196  * file. The values below are based on product and BKDG content.
 197  */
 198 #define DFLT_SCRUB_DRAM_RATE                    (0)
 199 #define DFLT_SCRUB_L2_RATE                              (0)
 200 #define DFLT_SCRUB_L3_RATE                              (0)
 201 #define DFLT_SCRUB_IC_RATE                              (0)
 202 #define DFLT_SCRUB_DC_RATE                              (0)
 203 #define DFLT_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
 204 #define DFLT_VRM_SLEW_RATE                              (5000)
 205
 206 /* AGESA nonsense: this header depends on the definitions above */
 207 /* Instantiate all solution relevant data. */
 208 #include <PlatformInstall.h>