src/mainboard/elmex/pcm205400/buildOpts.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /**
   4  * @file
   5  *
   6  * AMD User options selection for a Brazos platform solution system
   7  *
   8  * This file is placed in the user's platform directory and contains the
   9  * build option selections desired for that platform.
  10  *
  11  * For Information about this file, see @ref platforminstall.
  12  */
  13
  14 /* Select the CPU family. */
  15 #define INSTALL_FAMILY_14_SUPPORT TRUE
  16
  17 /* Select the cpu socket type. */
  18 #define INSTALL_FT1_SOCKET_SUPPORT      TRUE
  19
  20 /*
  21  * Agesa optional capabilities selection.
  22  * Uncomment and mark FALSE those features you wish to include in the build.
  23  * Comment out or mark TRUE those features you want to REMOVE from the build.
  24  */
  25
  26 #define BLDOPT_REMOVE_UDIMMS_SUPPORT                    FALSE
  27 #define BLDOPT_REMOVE_RDIMMS_SUPPORT                    TRUE
  28 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT                   FALSE
  29 #define BLDOPT_REMOVE_ECC_SUPPORT                               FALSE
  30 //#define BLDOPT_REMOVE_DCT_INTERLEAVE                  TRUE
  31 #define BLDOPT_REMOVE_BANK_INTERLEAVE                   FALSE
  32 #define BLDOPT_REMOVE_NODE_INTERLEAVE                   TRUE
  33 #define BLDOPT_REMOVE_PARALLEL_TRAINING                 FALSE
  34 #define BLDOPT_REMOVE_DQS_TRAINING                              FALSE
  35 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT              TRUE
  36 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT               TRUE
  37 #define BLDOPT_REMOVE_ACPI_PSTATES                              FALSE
  38         #define BLDCFG_REMOVE_ACPI_PSTATES_PPC                  FALSE
  39         #define BLDCFG_REMOVE_ACPI_PSTATES_PCT                  FALSE
  40         #define BLDCFG_REMOVE_ACPI_PSTATES_PSD                  FALSE
  41         #define BLDCFG_REMOVE_ACPI_PSTATES_PSS                  FALSE
  42         #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS                 FALSE
  43         #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT             FALSE
  44 #define BLDOPT_REMOVE_SRAT                                              FALSE
  45 #define BLDOPT_REMOVE_SLIT                                              FALSE
  46 #define BLDOPT_REMOVE_WHEA                                              FALSE
  47 #define BLDOPT_REMOVE_DMI                                               TRUE
  48 #define BLDOPT_REMOVE_HT_ASSIST                                 TRUE
  49 #define BLDOPT_REMOVE_ATM_MODE                                  TRUE
  50 //#define BLDOPT_REMOVE_MSG_BASED_C1E                   TRUE
  51 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT     TRUE
  52 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT               FALSE
  53 //#define BLDOPT_REMOVE_C6_STATE                                TRUE
  54 #define BLDOPT_REMOVE_GFX_RECOVERY                              TRUE
  55 #define BLDOPT_REMOVE_EARLY_SAMPLES                             TRUE
  56
  57 #define BLDCFG_VRM_CURRENT_LIMIT                                24000
  58 //#define BLDCFG_VRM_NB_CURRENT_LIMIT                   0
  59 #define BLDCFG_VRM_LOW_POWER_THRESHOLD                  24000
  60 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD               1
  61 #define BLDCFG_VRM_SLEW_RATE                                    5000
  62 //#define BLDCFG_VRM_NB_SLEW_RATE                               5000
  63 //#define BLDCFG_VRM_ADDITIONAL_DELAY                   0
  64 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY                0
  65 #define BLDCFG_VRM_HIGH_SPEED_ENABLE                    TRUE
  66 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE               FALSE
  67 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT                 6000
  68 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT    0
  69
  70 //#define BLDCFG_PROCESSOR_SCOPE_NAME0                  'C'
  71 //#define BLDCFG_PROCESSOR_SCOPE_NAME1                  '0'
  72 //#define BLDCFG_PROCESSOR_SCOPE_IN_SB                  FALSE
  73 #define BLDCFG_PLAT_NUM_IO_APICS                                3
  74 //#define BLDCFG_PLATFORM_C1E_MODE                              C1eModeDisabled
  75 //#define BLDCFG_PLATFORM_C1E_OPDATA                    0
  76 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1              0
  77 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2              0
  78 #define BLDCFG_PLATFORM_CSTATE_MODE                             CStateModeC6
  79 #define BLDCFG_PLATFORM_CSTATE_OPDATA                   0x840
  80 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
  81 //#define BLDCFG_PLATFORM_CPB_MODE                              CpbModeAuto
  82 #define BLDCFG_CORE_LEVELING_MODE                               CORE_LEVEL_LOWEST
  83 #define BLDCFG_AMD_PLATFORM_TYPE                                AMD_PLATFORM_MOBILE
  84 //#define BLDCFG_STARTING_BUSNUM                                0
  85 //#define BLDCFG_MAXIMUM_BUSNUM                                 0xf8
  86 //#define BLDCFG_ALLOCATED_BUSNUMS                              0x20
  87 //#define BLDCFG_PLATFORM_DEEMPHASIS_LIST               0
  88 //#define BLDCFG_BUID_SWAP_LIST                                 0
  89 //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST    0
  90 //#define BLDCFG_HTFABRIC_LIMITS_LIST                   0
  91 //#define BLDCFG_HTCHAIN_LIMITS_LIST                    0
  92 //#define BLDCFG_BUS_NUMBERS_LIST                               0
  93 //#define BLDCFG_IGNORE_LINK_LIST                               0
  94 //#define BLDCFG_LINK_SKIP_REGANG_LIST                  0
  95 //#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST             0
  96 //#define BLDCFG_USE_HT_ASSIST                                  TRUE
  97 //#define BLDCFG_USE_ATM_MODE                                   TRUE
  98 //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE             Nfcm
  99 #define BLDCFG_S3_LATE_RESTORE                                  TRUE
 100 //#define BLDCFG_USE_32_BYTE_REFRESH                    FALSE
 101 //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
 102 //#define BLDCFG_PLATFORM_POWER_POLICY_MODE             Performance
 103 //#define BLDCFG_SET_HTCRC_SYNC_FLOOD                   FALSE
 104 //#define BLDCFG_USE_UNIT_ID_CLUMPING                   FALSE
 105 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP             0
 106 #define BLDCFG_CFG_GNB_HD_AUDIO                                 FALSE
 107 //#define BLDCFG_CFG_ABM_SUPPORT                                FALSE
 108 //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE               0
 109 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL             0
 110 //#define BLDCFG_MEM_INIT_PSTATE                                0
 111 //#define BLDCFG_AMD_PSTATE_CAP_VALUE                   0
 112 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT               DDR1333_FREQUENCY
 113 #define BLDCFG_MEMORY_MODE_UNGANGED                             TRUE
 114 //#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE               TRUE
 115 //#define BLDCFG_MEMORY_QUADRANK_TYPE                   QUADRANK_UNBUFFERED
 116 #define BLDCFG_MEMORY_SODIMM_CAPABLE                    TRUE
 117 #define BLDCFG_MEMORY_LRDIMM_CAPABLE                    FALSE
 118 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING  TRUE
 119 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING  FALSE
 120 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING              FALSE
 121 #define BLDCFG_MEMORY_POWER_DOWN                                TRUE
 122 #define BLDCFG_POWER_DOWN_MODE                                  POWER_DOWN_BY_CHIP_SELECT
 123 //#define BLDCFG_ONLINE_SPARE                                   FALSE
 124 //#define BLDCFG_MEMORY_PARITY_ENABLE                   FALSE
 125 #define BLDCFG_BANK_SWIZZLE                                             TRUE
 126 #define BLDCFG_TIMING_MODE_SELECT                               TIMING_MODE_AUTO
 127 #define BLDCFG_MEMORY_CLOCK_SELECT                              DDR1333_FREQUENCY
 128 #define BLDCFG_DQS_TRAINING_CONTROL                             TRUE
 129 #define BLDCFG_IGNORE_SPD_CHECKSUM                              FALSE
 130 #define BLDCFG_USE_BURST_MODE                                   FALSE
 131 #define BLDCFG_MEMORY_ALL_CLOCKS_ON                             FALSE
 132 //#define BLDCFG_ENABLE_ECC_FEATURE                             TRUE
 133 //#define BLDCFG_ECC_REDIRECTION                                FALSE
 134 //#define BLDCFG_SCRUB_DRAM_RATE                                0
 135 //#define BLDCFG_SCRUB_L2_RATE                                  0
 136 //#define BLDCFG_SCRUB_L3_RATE                                  0
 137 //#define BLDCFG_SCRUB_IC_RATE                                  0
 138 //#define BLDCFG_SCRUB_DC_RATE                                  0
 139 //#define BLDCFG_ECC_SYNC_FLOOD                                 0
 140 //#define BLDCFG_ECC_SYMBOL_SIZE                                0
 141 //#define BLDCFG_1GB_ALIGN                                              FALSE
 142 #define BLDCFG_UMA_ALLOCATION_MODE                              UMA_AUTO
 143 #define BLDCFG_UMA_ALLOCATION_SIZE                              0
 144 #define BLDCFG_UMA_ABOVE4G_SUPPORT                              FALSE
 145 #define BLDCFG_UMA_ALIGNMENT                                    NO_UMA_ALIGNED
 146 #define BLDCFG_HEAP_DRAM_ADDRESS                                0xB0000
 147 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
 148
 149 /*
 150  * Agesa configuration values selection.
 151  * Uncomment and specify the value for the configuration options
 152  * needed by the system.
 153  */
 154 #include <AGESA.h>
 155
 156 /* Include the files that instantiate the configuration definitions. */
 157
 158 #include "cpuRegisters.h"
 159 #include "cpuFamRegisters.h"
 160 #include "cpuFamilyTranslation.h"
 161 #include "AdvancedApi.h"
 162 #include "heapManager.h"
 163 #include "CreateStruct.h"
 164 #include "cpuFeatures.h"
 165 #include "Table.h"
 166 #include "cpuEarlyInit.h"
 167 #include "cpuLateInit.h"
 168 #include "GnbInterface.h"
 169
 170 /* MEMORY_BUS_SPEED */
 171 #define DDR400_FREQUENCY                                200 ///< DDR 400
 172 #define DDR533_FREQUENCY                                266 ///< DDR 533
 173 #define DDR667_FREQUENCY                                333 ///< DDR 667
 174 #define DDR800_FREQUENCY                                400 ///< DDR 800
 175 #define DDR1066_FREQUENCY                               533 ///< DDR 1066
 176 #define DDR1333_FREQUENCY                               667 ///< DDR 1333
 177 #define DDR1600_FREQUENCY                               800 ///< DDR 1600
 178 #define DDR1866_FREQUENCY                               933 ///< DDR 1866
 179 #define UNSUPPORTED_DDR_FREQUENCY               934 ///< Highest limit of DDR frequency
 180
 181 /* QUANDRANK_TYPE */
 182 #define QUADRANK_REGISTERED                             0 ///< Quadrank registered DIMM
 183 #define QUADRANK_UNBUFFERED                             1 ///< Quadrank unbuffered DIMM
 184
 185 /* USER_MEMORY_TIMING_MODE */
 186 #define TIMING_MODE_AUTO                                0 ///< Use best rate possible
 187 #define TIMING_MODE_LIMITED                             1 ///< Set user top limit
 188 #define TIMING_MODE_SPECIFIC                    2 ///< Set user specified speed
 189
 190 /* POWER_DOWN_MODE */
 191 #define POWER_DOWN_BY_CHANNEL                   0 ///< Channel power down mode
 192 #define POWER_DOWN_BY_CHIP_SELECT               1 ///< Chip select power down mode
 193
 194 // The following definitions specify the default values for various parameters in which there are
 195 // no clearly defined defaults to be used in the common file.   The values below are based on product
 196 // and BKDG content, please consult the AGESA Memory team for consultation.
 197 #define DFLT_SCRUB_DRAM_RATE                    (0)
 198 #define DFLT_SCRUB_L2_RATE                              (0)
 199 #define DFLT_SCRUB_L3_RATE                              (0)
 200 #define DFLT_SCRUB_IC_RATE                              (0)
 201 #define DFLT_SCRUB_DC_RATE                              (0)
 202 #define DFLT_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
 203 #define DFLT_VRM_SLEW_RATE                              (5000)
 204
 205 // Instantiate all solution relevant data.
 206 #include <PlatformInstall.h>