2 # This file is part of the coreboot project.
4 # Copyright
(C
) 2015 Damien Zammit
<damien@zamaudio.com
>
5 # Copyright
(C
) 2018 Arthur Heymans
<arthur@aheymans.xyz
>
7 # This program is free software
; you can redistribute it
and/or modify
8 # it under the terms of the GNU General Public License
as published by
9 # the Free Software Foundation
; either version
2 of the License
, or
10 #
(at your option
) any later version.
12 # This program is distributed in the hope that it will be useful
,
13 # but WITHOUT ANY WARRANTY
; without even the implied warranty of
14 # MERCHANTABILITY
or FITNESS
FOR A PARTICULAR PURPOSE. See the
15 # GNU General Public License
for more details.
18 chip northbridge
/intel
/x4x # Northbridge
19 device cpu_cluster
0 on # APIC cluster
20 chip cpu
/intel
/socket_LGA775
23 chip cpu
/intel
/model_1067x # CPU
24 device lapic
0xACAC off
end
27 device domain
0 on # PCI domain
28 device pci
0.0 on
end # Host Bridge
29 device pci
1.0 on
end # PEG
30 device pci
2.0 off
end # Integrated graphics controller
31 device pci
2.1 off
end # Integrated graphics controller
2
32 device pci
3.0 off
end #
ME
33 device pci
3.1 off
end #
ME
34 device pci
3.2 off
end #
ME
35 device pci
3.3 off
end #
ME
36 device pci
6.0 on
end # PEG
2
37 chip southbridge
/intel
/i82801jx # Southbridge
38 register
"gpe0_en" = "0x40"
41 register
"sata_port_map" = "0x3f"
42 register
"sata_clock_request" = "0"
43 register
"sata_traffic_monitor" = "0"
45 # Enable PCIe ports
0,2,3 as slots.
46 register
"pcie_slot_implemented" = "0x31"
48 device pci
19.0 off
end # GBE
49 device pci
1a
.0 on
end # USB
50 device pci
1a
.1 on
end # USB
51 device pci
1a
.2 on
end # USB
52 device pci
1a
.7 on
end # USB
53 device pci
1b
.0 on
end # Audio
54 device pci
1c
.0 on
end # PCIe
1
55 device pci
1c
.1 off
end # PCIe
2
56 device pci
1c
.2 off
end # PCIe
3
57 device pci
1c
.3 off
end # PCIe
4
58 device pci
1c
.4 on
end # PCIe
5 MARVEL IDE
59 device pci
1c
.5 on
end # PCIe
6
60 device pci
1d
.0 on
end # USB
61 device pci
1d
.1 on
end # USB
62 device pci
1d
.2 on
end # USB
63 device pci
1d
.7 on
end # USB
64 device pci
1e
.0 on
end # PCI bridge
65 device pci
1f
.0 on # LPC bridge
66 chip superio
/winbond
/w83667hg
-a # Super I
/O
67 device pnp
2e
.0 on # FDC
75 device pnp
2e
.1 off
end # LPT1
76 device pnp
2e
.2 on # COM1
80 device pnp
2e
.3 off
end # COM2
81 device pnp
2e
.5 on # PS
/2 keyboard
& mouse
87 device pnp
2e
.106 off
end # SPI1
88 device pnp
2e
.107 off
end # GPIO6
89 device pnp
2e
.207 off
end # GPIO7
90 device pnp
2e
.307 on # GPIO8
94 device pnp
2e
.407 off
end # GPIO9
95 device pnp
2e
.8 off
end # WDT
96 device pnp
2e
.108 off
end # GPIO1
97 device pnp
2e
.9 off
end # GPIO2
98 device pnp
2e
.109 on
end # GPIO3
99 device pnp
2e
.209 on # GPIO4
103 device pnp
2e
.309 on
end # GPIO5
104 device pnp
2e.a on # ACPI
105 irq
0xe4 = 0x10 #
3VSBSW# enable
109 device pnp
2e.b on # HW Monitor
112 # IRQ purposefully
not assigned
to prevent lockups
114 device pnp
2e.c on
end # PECI
115 device pnp
2e.d on
end # VID_BUSSEL
116 device pnp
2e.f on
end # GPIO_PP_OD
119 device pci
1f
.1 off
end # PATA
/IDE
120 device pci
1f
.2 on
end # SATA
121 device pci
1f
.3 on
end # SMbus
122 device pci
1f
.4 off
end
123 device pci
1f
.5 on
end # IDE
124 device pci
1f
.6 off
end