src/soc/intel/elkhartlake/fsp_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 #include <assert.h>
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <fsp/api.h>
   6 #include <fsp/ppi/mp_service_ppi.h>
   7 #include <fsp/util.h>
   8 #include <intelblocks/lpss.h>
   9 #include <intelblocks/mp_init.h>
  10 #include <intelblocks/xdci.h>
  11 #include <intelpch/lockdown.h>
  12 #include <soc/intel/common/vbt.h>
  13 #include <soc/pci_devs.h>
  14 #include <soc/ramstage.h>
  15 #include <soc/soc_chip.h>
  16 #include <string.h>
  17
  18 /* SATA DEVSLP idle timeout default values */
  19 #define DEF_DMVAL               15
  20 #define DEF_DITOVAL_MS          625
  21
  22 /* Native function controls pads termination */
  23 #define GPIO_TERM_NATIVE        0x1F
  24
  25 /* PM related values */
  26 /* Imon offset is defined in 1/1000 increments */
  27 #define IMON_OFFSET     1
  28 /* Policy Imon slope is defined in 1/100 increments */
  29 #define IMON_SLOPE      100
  30 /* Thermal Design Current current limit in 1/8A units */
  31 #define TDC_CURRENT_LIMIT_MAX   112
  32 /* AcLoadline in 1/100 mOhms */
  33 #define AC_LOADLINE_LANE_0_MAX  112
  34 #define AC_LOADLINE_LANE_1_MAX  3
  35 /* DcLoadline in 1/100 mOhms */
  36 #define DC_LOADLINE_LANE_0_MAX  92
  37 #define DC_LOADLINE_LANE_1_MAX  3
  38 /* VR Icc Max limit. 0-255A in 1/4 A units */
  39 #define ICC_LIMIT_MAX   104
  40 /* Core Ratio Limit: For overclocking part: LFM to Fused */
  41 #define CORE_RATIO_LIMIT        0x13
  42
  43 /*
  44  * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
  45  * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
  46  * In order to ensure that mainboard setting does not disable L1 substates
  47  * incorrectly, chip config parameter values are offset by 1 with 0 meaning
  48  * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
  49  * value is set in fsp_params.
  50  * 0: Use FSP UPD default
  51  * 1: Disable L1 substates
  52  * 2: Use L1.1
  53  * 3: Use L1.2 (FSP UPD default)
  54  */
  55 static int get_l1_substate_control(enum L1_substates_control ctl)
  56 {
  57         if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
  58                 ctl = L1_SS_L1_2;
  59         return ctl - 1;
  60 }
  61
  62 static void parse_devicetree(FSP_S_CONFIG *params)
  63 {
  64         const struct soc_intel_elkhartlake_config *config = config_of_soc();
  65
  66         /* LPSS controllers configuration */
  67
  68         /* I2C */
  69         _Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >=
  70                         ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!");
  71         memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode,
  72                 sizeof(config->SerialIoI2cMode));
  73
  74         _Static_assert(ARRAY_SIZE(params->PchSerialIoI2cPadsTermination) >=
  75                         ARRAY_SIZE(config->SerialIoI2cPadsTermination),
  76                         "copy buffer overflow!");
  77         memcpy(params->PchSerialIoI2cPadsTermination, config->SerialIoI2cPadsTermination,
  78                 sizeof(config->SerialIoI2cPadsTermination));
  79
  80         params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09;        //GPIO native mode for GPP_H9
  81         params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08;        //GPIO native mode for GPP_H8
  82
  83         /* GSPI */
  84         _Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >=
  85                         ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!");
  86         memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode,
  87                 sizeof(config->SerialIoGSpiMode));
  88
  89         _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsEnable) >=
  90                         ARRAY_SIZE(config->SerialIoGSpiCsEnable), "copy buffer overflow!");
  91         memcpy(params->SerialIoSpiCsEnable, config->SerialIoGSpiCsEnable,
  92                 sizeof(config->SerialIoGSpiCsEnable));
  93
  94         _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >=
  95                         ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!");
  96         memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode,
  97                 sizeof(config->SerialIoGSpiCsMode));
  98
  99         _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >=
 100                         ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!");
 101         memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState,
 102                 sizeof(config->SerialIoGSpiCsState));
 103
 104         params->SerialIoSpiCsPolarity[2] = 0;
 105
 106         /* UART */
 107         _Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >=
 108                         ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!");
 109         memcpy(params->SerialIoUartMode, config->SerialIoUartMode,
 110                 sizeof(config->SerialIoUartMode));
 111
 112         _Static_assert(ARRAY_SIZE(params->SerialIoUartDmaEnable) >=
 113                         ARRAY_SIZE(config->SerialIoUartDmaEnable), "copy buffer overflow!");
 114         memcpy(params->SerialIoUartDmaEnable, config->SerialIoUartDmaEnable,
 115                 sizeof(config->SerialIoUartDmaEnable));
 116
 117         params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F;    //GPIO native mode for GPP_T15
 118         params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E;    //GPIO native mode for GPP_T14
 119         params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C;     //GPIO native mode for GPP_T12
 120         params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D;     //GPIO native mode for GPP_T13
 121
 122         /* Provide correct UART number for FSP debug logs */
 123         params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
 124 }
 125
 126 /* UPD parameters to be initialized before SiliconInit */
 127 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 128 {
 129         unsigned int i;
 130         struct device *dev;
 131         FSP_S_CONFIG *params = &supd->FspsConfig;
 132         struct soc_intel_elkhartlake_config *config = config_of_soc();
 133
 134         /* Parse device tree and fill in FSP UPDs */
 135         parse_devicetree(params);
 136
 137         /* Load VBT before devicetree-specific config. */
 138         params->GraphicsConfigPtr = (uintptr_t)vbt_get();
 139
 140         /* Check if IGD is present and fill Graphics init param accordingly */
 141         params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 142
 143         /* Display config */
 144         params->DdiPortAHpd = config->DdiPortAHpd;
 145         params->DdiPortADdc = config->DdiPortADdc;
 146         params->DdiPortCHpd = config->DdiPortCHpd;
 147         params->DdiPortCDdc = config->DdiPortCDdc;
 148
 149         /* Use coreboot MP PPI services if Kconfig is enabled */
 150         if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
 151                 params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
 152
 153         /* Chipset Lockdown */
 154         if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
 155                 params->PchLockDownGlobalSmi = 0;
 156                 params->PchLockDownBiosLock = 0;
 157                 params->PchLockDownBiosInterface = 0;
 158                 params->PchWriteProtectionEnable[0] = 0;
 159                 params->PchUnlockGpioPads = 1;
 160                 params->RtcMemoryLock = 0;
 161         } else {
 162                 params->PchLockDownGlobalSmi = 1;
 163                 params->PchLockDownBiosLock = 1;
 164                 params->PchLockDownBiosInterface = 1;
 165                 params->PchWriteProtectionEnable[0] = 1;
 166                 params->PchUnlockGpioPads = 0;
 167                 params->RtcMemoryLock = 1;
 168         }
 169
 170         /* Disable PAVP */
 171         params->PavpEnable = 0;
 172
 173         /* Legacy 8254 timer support */
 174         params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
 175         params->Enable8254ClockGatingOnS3 = 1;
 176
 177         /* PCH Master Gating Control */
 178         params->PchPostMasterClockGating = 1;
 179         params->PchPostMasterPowerGating = 1;
 180
 181         /* HECI */
 182         params->Heci3Enabled = config->Heci3Enable;
 183
 184         /* USB configuration */
 185         for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 186                 params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
 187                 params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
 188                 params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
 189                 params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
 190                 params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
 191                 params->Usb2OverCurrentPin[i] = config->usb2_ports[i].enable ?
 192                         config->usb2_ports[i].ocpin : 0xff;
 193         }
 194
 195         for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 196                 params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 197                 params->Usb3OverCurrentPin[i] = config->usb3_ports[i].enable ?
 198                         config->usb3_ports[i].ocpin : 0xff;
 199                 if (config->usb3_ports[i].tx_de_emp) {
 200                         params->Usb3HsioTxDeEmphEnable[i] = 1;
 201                         params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
 202                 }
 203                 if (config->usb3_ports[i].tx_downscale_amp) {
 204                         params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
 205                         params->Usb3HsioTxDownscaleAmp[i] =
 206                                 config->usb3_ports[i].tx_downscale_amp;
 207                 }
 208         }
 209
 210         params->UsbClockGatingEnable = 1;
 211         params->UsbPowerGatingEnable = 1;
 212
 213         /* Enable xDCI controller if enabled in devicetree and allowed */
 214         dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 215         if (dev) {
 216                 if (!xdci_can_enable())
 217                         dev->enabled = 0;
 218
 219                 params->XdciEnable = dev->enabled;
 220         } else {
 221                 params->XdciEnable = 0;
 222         }
 223
 224         /* PCIe root ports config */
 225         for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
 226                 params->PcieRpClkReqDetect[i] =
 227                         !config->PcieRpClkReqDetectDisable[i];
 228                 params->PcieRpL1Substates[i] =
 229                         get_l1_substate_control(config->PcieRpL1Substates[i]);
 230                 params->PcieRpLtrEnable[i] = !config->PcieRpLtrDisable[i];
 231                 params->PcieRpAdvancedErrorReporting[i] =
 232                         !config->PcieRpAdvancedErrorReportingDisable[i];
 233                 params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
 234                 params->PciePtm[i] = config->PciePtm[i];
 235                 params->PcieRpLtrMaxNoSnoopLatency[i] = 0x1003;
 236                 params->PcieRpLtrMaxSnoopLatency[i] = 0x1003;
 237                 /* Virtual Channel 1 to Traffic Class mapping */
 238                 params->PcieRpVc1TcMap[i] = 0x60;
 239         }
 240
 241         /* SATA config */
 242         params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
 243         if (params->SataEnable) {
 244                 params->SataMode = config->SataMode;
 245                 params->SataSalpSupport = config->SataSalpSupport;
 246                 params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
 247
 248                 for (i = 0; i < CONFIG_MAX_SATA_PORTS; i++) {
 249                         params->SataPortsEnable[i] = config->SataPortsEnable[i];
 250                         params->SataPortsDevSlp[i] = config->SataPortsDevSlp[i];
 251                         if (config->SataPortsEnableDitoConfig[i]) {
 252                                 params->SataPortsDmVal[i] =
 253                                         config->SataPortsDmVal[i] ? : DEF_DMVAL;
 254                                 params->SataPortsDitoVal[i] =
 255                                         config->SataPortsDitoVal[i] ? : DEF_DITOVAL_MS;
 256                         }
 257                 }
 258         }
 259
 260         /* SDCard config */
 261         params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
 262         if (params->ScsSdCardEnabled) {
 263                 params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
 264                 params->SdCardGpioCmdPadTermination = GPIO_TERM_NATIVE;
 265                 params->SdCardGpioDataPadTermination[0] = GPIO_TERM_NATIVE;
 266                 params->SdCardGpioDataPadTermination[1] = GPIO_TERM_NATIVE;
 267                 params->SdCardGpioDataPadTermination[2] = GPIO_TERM_NATIVE;
 268                 params->SdCardGpioDataPadTermination[3] = GPIO_TERM_NATIVE;
 269         }
 270
 271         /* eMMC config */
 272         params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
 273         if (params->ScsEmmcEnabled) {
 274                 params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
 275                 params->ScsEmmcDdr50Enabled = config->ScsEmmcDdr50Enabled;
 276         }
 277
 278         /* Thermal config */
 279         dev = pcidev_path_on_root(SA_DEVFN_DPTF);
 280         params->Device4Enable = is_dev_enabled(dev);
 281         params->ProcHotResponse = 0x0;  //Disable PROCHOT response
 282         /* Thermal sensor (TS) target width */
 283         params->DmiTS0TW = 3;
 284         params->DmiTS1TW = 2;
 285         params->DmiTS2TW = 1;
 286         /* Enable memory thermal throttling by default */
 287         if (!config->MemoryThermalThrottlingDisable) {
 288                 params->PchMemoryPmsyncEnable[0] = 1;
 289                 params->PchMemoryPmsyncEnable[1] = 1;
 290                 params->PchMemoryC0TransmitEnable[0] = 1;
 291                 params->PchMemoryC0TransmitEnable[1] = 1;
 292         }
 293
 294         /* TccActivationOffset config */
 295         params->TccActivationOffset = config->tcc_offset;
 296         params->TccOffsetClamp = config->tcc_offset_clamp;
 297         params->TccOffsetLock = 0x1;    //lock Tcc Offset register
 298
 299         /* Power management config */
 300         params->ImonSlope[0] = IMON_SLOPE;
 301         params->ImonOffset[0] = IMON_OFFSET;
 302         params->TdcCurrentLimit[0] = TDC_CURRENT_LIMIT_MAX;
 303         params->AcLoadline[0] = AC_LOADLINE_LANE_0_MAX;
 304         params->DcLoadline[0] = DC_LOADLINE_LANE_0_MAX;
 305         params->AcLoadline[1] = AC_LOADLINE_LANE_1_MAX;
 306         params->DcLoadline[1] = DC_LOADLINE_LANE_1_MAX;
 307         params->IccMax[0] = ICC_LIMIT_MAX;
 308         params->OneCoreRatioLimit = CORE_RATIO_LIMIT;
 309         params->TwoCoreRatioLimit = CORE_RATIO_LIMIT;
 310         params->ThreeCoreRatioLimit = CORE_RATIO_LIMIT;
 311         params->FourCoreRatioLimit = CORE_RATIO_LIMIT;
 312         params->FiveCoreRatioLimit = CORE_RATIO_LIMIT;
 313         params->SixCoreRatioLimit = CORE_RATIO_LIMIT;
 314         params->SevenCoreRatioLimit = CORE_RATIO_LIMIT;
 315         params->EightCoreRatioLimit = CORE_RATIO_LIMIT;
 316         params->PsysPmax = 0;   //Set max platform power to auto profile
 317         params->Custom1TurboActivationRatio = 0;
 318         params->Custom2TurboActivationRatio = 0;
 319         params->Custom3TurboActivationRatio = 0;
 320         params->PchPwrOptEnable = 0x1;  //Enable PCH DMI Power Optimizer
 321         params->TStates = 0x0;  //Disable T state
 322         params->PkgCStateLimit = 0x7;   //Set C state limit to C9
 323         params->FastPkgCRampDisable[0] = 0x1;
 324         params->SlowSlewRate[0] = 0x1;
 325         params->MaxRatio = 0x8; //Set max P state ratio
 326         params->PchEspiLgmrEnable = 0;
 327         params->PchPmPwrBtnOverridePeriod = config->PchPmPwrBtnOverridePeriod;
 328         params->PchS0ixAutoDemotion = 0;
 329         params->PmcV1p05PhyExtFetControlEn = 0x1;
 330         params->PmcV1p05IsExtFetControlEn = 0x1;
 331         /* FIVR config */
 332         params->PchFivrExtV1p05RailEnabledStates = 0x1E;
 333         params->PchFivrExtV1p05RailSupportedVoltageStates = 0x2;
 334         params->PchFivrExtVnnRailEnabledStates = 0x1E;
 335         params->PchFivrExtVnnRailSupportedVoltageStates = 0xE;
 336         params->PchFivrExtVnnRailSxEnabledStates = 0x1C;
 337         params->PchFivrVccinAuxLowToHighCurModeVolTranTime = 0x0C;
 338         params->PchFivrVccinAuxRetToHighCurModeVolTranTime = 0x36;
 339         params->PchFivrVccinAuxRetToLowCurModeVolTranTime = 0x2B;
 340         params->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0x0096;
 341         params->FivrSpreadSpectrum = 0xF;
 342
 343         /* FuSa (Functional Safety) config */
 344         if (!config->FuSaEnable) {
 345                 params->DisplayFusaConfigEnable = 0;
 346                 params->GraphicFusaConfigEnable = 0;
 347                 params->OpioFusaConfigEnable = 0;
 348                 params->PsfFusaConfigEnable = 0;
 349         }
 350
 351         /* Override/Fill FSP Silicon Param for mainboard */
 352         mainboard_silicon_init_params(params);
 353 }
 354
 355 /* Mainboard GPIO Configuration */
 356 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 357 {
 358         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 359 }