| blob | 25030aa8146f320a5b3b702e51890f2457a90939 |
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
20 /* DefinitionBlock Statement */
21 DefinitionBlock (
22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
25 "ASROCK", /* OEMID */
26 "COREBOOT", /* TABLE ID */
27 0x00010001 /* OEM Revision */
28 )
29 { /* Start of ASL file */
30 /* #include <arch/i386/acpi/debug.asl> */ /* Include global debug methods if needed */
32 /* Data to be patched by the BIOS during POST */
33 /* FIXME the patching is not done yet! */
34 /* Memory related values */
35 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
36 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
37 Name(PBLN, 0x0) /* Length of BIOS area */
39 Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
40 Name(HPBA, 0xFED00000) /* Base address of HPET table */
42 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
44 /* USB overcurrent mapping pins. */
45 Name(UOM0, 0)
46 Name(UOM1, 2)
47 Name(UOM2, 0)
48 Name(UOM3, 7)
49 Name(UOM4, 2)
50 Name(UOM5, 2)
51 Name(UOM6, 6)
52 Name(UOM7, 2)
53 Name(UOM8, 6)
54 Name(UOM9, 6)
56 /* Some global data */
57 Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
58 Name(OSV, Ones) /* Assume nothing */
59 Name(PMOD, One) /* Assume APIC */
61 /*
62 * Processor Object
63 *
64 */
65 Scope (\_PR) { /* define processor scope */
66 Processor(
67 C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */
68 0, /* Unique number for this processor */
69 0x810, /* PBLK system I/O address !hardcoded! */
70 0x06 /* PBLKLEN for boot processor */
71 ) {
72 }
74 Processor(
75 C001, /* name space name */
76 1, /* Unique number for this processor */
77 0x810, /* PBLK system I/O address !hardcoded! */
78 0x06 /* PBLKLEN for boot processor */
79 ) {
80 }
81 Processor(
82 C002, /* name space name */
83 2, /* Unique number for this processor */
84 0x810, /* PBLK system I/O address !hardcoded! */
85 0x06 /* PBLKLEN for boot processor */
86 ) {
87 }
88 Processor(
89 C003, /* name space name */
90 3, /* Unique number for this processor */
91 0x810, /* PBLK system I/O address !hardcoded! */
92 0x06 /* PBLKLEN for boot processor */
93 ) {
94 }
95 } /* End _PR scope */
97 /* PIC IRQ mapping registers, C00h-C01h. */
98 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
99 Field(PRQM, ByteAcc, NoLock, Preserve) {
100 PRQI, 0x00000008,
101 PRQD, 0x00000008, /* Offset: 1h */
102 }
103 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
104 PIRA, 0x00000008, /* Index 0 */
105 PIRB, 0x00000008, /* Index 1 */
106 PIRC, 0x00000008, /* Index 2 */
107 PIRD, 0x00000008, /* Index 3 */
108 PIRE, 0x00000008, /* Index 4 */
109 PIRF, 0x00000008, /* Index 5 */
110 PIRG, 0x00000008, /* Index 6 */
111 PIRH, 0x00000008, /* Index 7 */
112 }
114 /* PCI Error control register */
115 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
116 Field(PERC, ByteAcc, NoLock, Preserve) {
117 SENS, 0x00000001,
118 PENS, 0x00000001,
119 SENE, 0x00000001,
120 PENE, 0x00000001,
121 }
123 /* Client Management index/data registers */
124 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
125 Field(CMT, ByteAcc, NoLock, Preserve) {
126 CMTI, 8,
127 /* Client Management Data register */
128 G64E, 1,
129 G64O, 1,
130 G32O, 2,
131 , 2,
132 GPSL, 2,
133 }
135 /* GPM Port register */
136 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
137 Field(GPT, ByteAcc, NoLock, Preserve) {
138 GPB0,1,
139 GPB1,1,
140 GPB2,1,
141 GPB3,1,
142 GPB4,1,
143 GPB5,1,
144 GPB6,1,
145 GPB7,1,
146 }
148 /* Flash ROM program enable register */
149 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
150 Field(FRE, ByteAcc, NoLock, Preserve) {
151 , 0x00000006,
152 FLRE, 0x00000001,
153 }
155 /* PM2 index/data registers */
156 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
157 Field(PM2R, ByteAcc, NoLock, Preserve) {
158 PM2I, 0x00000008,
159 PM2D, 0x00000008,
160 }
162 /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
163 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
164 Field(PIOR, ByteAcc, NoLock, Preserve) {
165 PIOI, 0x00000008,
166 PIOD, 0x00000008,
167 }
168 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
169 Offset(0x00), /* MiscControl */
170 , 1,
171 T1EE, 1,
172 T2EE, 1,
173 Offset(0x01), /* MiscStatus */
174 , 1,
175 T1E, 1,
176 T2E, 1,
177 Offset(0x04), /* SmiWakeUpEventEnable3 */
178 , 7,
179 SSEN, 1,
180 Offset(0x07), /* SmiWakeUpEventStatus3 */
181 , 7,
182 CSSM, 1,
183 Offset(0x10), /* AcpiEnable */
184 , 6,
185 PWDE, 1,
186 Offset(0x1C), /* ProgramIoEnable */
187 , 3,
188 MKME, 1,
189 IO3E, 1,
190 IO2E, 1,
191 IO1E, 1,
192 IO0E, 1,
193 Offset(0x1D), /* IOMonitorStatus */
194 , 3,
195 MKMS, 1,
196 IO3S, 1,
197 IO2S, 1,
198 IO1S, 1,
199 IO0S,1,
200 Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */
201 APEB, 16,
202 Offset(0x36), /* GEvtLevelConfig */
203 , 6,
204 ELC6, 1,
205 ELC7, 1,
206 Offset(0x37), /* GPMLevelConfig0 */
207 , 3,
208 PLC0, 1,
209 PLC1, 1,
210 PLC2, 1,
211 PLC3, 1,
212 PLC8, 1,
213 Offset(0x38), /* GPMLevelConfig1 */
214 , 1,
215 PLC4, 1,
216 PLC5, 1,
217 , 1,
218 PLC6, 1,
219 PLC7, 1,
220 Offset(0x3B), /* PMEStatus1 */
221 GP0S, 1,
222 GM4S, 1,
223 GM5S, 1,
224 APS, 1,
225 GM6S, 1,
226 GM7S, 1,
227 GP2S, 1,
228 STSS, 1,
229 Offset(0x55), /* SoftPciRst */
230 SPRE, 1,
231 , 1,
232 , 1,
233 PNAT, 1,
234 PWMK, 1,
235 PWNS, 1,
237 /* Offset(0x61), */ /* Options_1 */
238 /* ,7, */
239 /* R617,1, */
241 Offset(0x65), /* UsbPMControl */
242 , 4,
243 URRE, 1,
244 Offset(0x68), /* MiscEnable68 */
245 , 3,
246 TMTE, 1,
247 , 1,
248 Offset(0x92), /* GEVENTIN */
249 , 7,
250 E7IS, 1,
251 Offset(0x96), /* GPM98IN */
252 G8IS, 1,
253 G9IS, 1,
254 Offset(0x9A), /* EnhanceControl */
255 ,7,
256 HPDE, 1,
257 Offset(0xA8), /* PIO7654Enable */
258 IO4E, 1,
259 IO5E, 1,
260 IO6E, 1,
261 IO7E, 1,
262 Offset(0xA9), /* PIO7654Status */
263 IO4S, 1,
264 IO5S, 1,
265 IO6S, 1,
266 IO7S, 1,
267 }
269 /* PM1 Event Block
270 * First word is PM1_Status, Second word is PM1_Enable
271 */
272 OperationRegion(P1EB, SystemIO, APEB, 0x04)
273 Field(P1EB, ByteAcc, NoLock, Preserve) {
274 TMST, 1,
275 , 3,
276 BMST, 1,
277 GBST, 1,
278 Offset(0x01),
279 PBST, 1,
280 , 1,
281 RTST, 1,
282 , 3,
283 PWST, 1,
284 SPWS, 1,
285 Offset(0x02),
286 TMEN, 1,
287 , 4,
288 GBEN, 1,
289 Offset(0x03),
290 PBEN, 1,
291 , 1,
292 RTEN, 1,
293 , 3,
294 PWDA, 1,
295 }
297 Scope(\_SB) {
298 /* PCIe Configuration Space for 16 busses */
299 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
300 Field(PCFG, ByteAcc, NoLock, Preserve) {
301 /* Byte offsets are computed using the following technique:
302 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
303 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
304 */
305 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
306 STB5, 32,
307 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
308 PT0D, 1,
309 PT1D, 1,
310 PT2D, 1,
311 PT3D, 1,
312 PT4D, 1,
313 PT5D, 1,
314 PT6D, 1,
315 PT7D, 1,
316 PT8D, 1,
317 PT9D, 1,
318 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
319 SBIE, 1,
320 SBME, 1,
321 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
322 SBRI, 8,
323 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
324 SBB1, 32,
325 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
326 ,14,
327 P92E, 1, /* Port92 decode enable */
328 }
330 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
331 Field(SB5, AnyAcc, NoLock, Preserve){
332 /* Port 0 */
333 Offset(0x120), /* Port 0 Task file status */
334 P0ER, 1,
335 , 2,
336 P0DQ, 1,
337 , 3,
338 P0BY, 1,
339 Offset(0x128), /* Port 0 Serial ATA status */
340 P0DD, 4,
341 , 4,
342 P0IS, 4,
343 Offset(0x12C), /* Port 0 Serial ATA control */
344 P0DI, 4,
345 Offset(0x130), /* Port 0 Serial ATA error */
346 , 16,
347 P0PR, 1,
349 /* Port 1 */
350 offset(0x1A0), /* Port 1 Task file status */
351 P1ER, 1,
352 , 2,
353 P1DQ, 1,
354 , 3,
355 P1BY, 1,
356 Offset(0x1A8), /* Port 1 Serial ATA status */
357 P1DD, 4,
358 , 4,
359 P1IS, 4,
360 Offset(0x1AC), /* Port 1 Serial ATA control */
361 P1DI, 4,
362 Offset(0x1B0), /* Port 1 Serial ATA error */
363 , 16,
364 P1PR, 1,
366 /* Port 2 */
367 Offset(0x220), /* Port 2 Task file status */
368 P2ER, 1,
369 , 2,
370 P2DQ, 1,
371 , 3,
372 P2BY, 1,
373 Offset(0x228), /* Port 2 Serial ATA status */
374 P2DD, 4,
375 , 4,
376 P2IS, 4,
377 Offset(0x22C), /* Port 2 Serial ATA control */
378 P2DI, 4,
379 Offset(0x230), /* Port 2 Serial ATA error */
380 , 16,
381 P2PR, 1,
383 /* Port 3 */
384 Offset(0x2A0), /* Port 3 Task file status */
385 P3ER, 1,
386 , 2,
387 P3DQ, 1,
388 , 3,
389 P3BY, 1,
390 Offset(0x2A8), /* Port 3 Serial ATA status */
391 P3DD, 4,
392 , 4,
393 P3IS, 4,
394 Offset(0x2AC), /* Port 3 Serial ATA control */
395 P3DI, 4,
396 Offset(0x2B0), /* Port 3 Serial ATA error */
397 , 16,
398 P3PR, 1,
399 }
400 }
403 #include "acpi/routing.asl"
405 Scope(\_SB) {
407 Method(CkOT, 0){
409 if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
411 if(CondRefOf(\_OSI,Local1))
412 {
413 Store(1, OSTP) /* Assume some form of XP */
414 if (\_OSI("Windows 2006")) /* Vista */
415 {
416 Store(2, OSTP)
417 }
418 } else {
419 If(WCMP(\_OS,"Linux")) {
420 Store(3, OSTP) /* Linux */
421 } Else {
422 Store(4, OSTP) /* Gotta be WinCE */
423 }
424 }
425 Return(OSTP)
426 }
428 Method(_PIC, 0x01, NotSerialized)
429 {
430 If (Arg0)
431 {
432 \_SB.CIRQ()
433 }
434 Store(Arg0, PMOD)
435 }
436 Method(CIRQ, 0x00, NotSerialized){
437 Store(0, PIRA)
438 Store(0, PIRB)
439 Store(0, PIRC)
440 Store(0, PIRD)
441 Store(0, PIRE)
442 Store(0, PIRF)
443 Store(0, PIRG)
444 Store(0, PIRH)
445 }
447 Name(IRQB, ResourceTemplate(){
448 IRQ(Level,ActiveLow,Shared){15}
449 })
451 Name(IRQP, ResourceTemplate(){
452 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
453 })
455 Name(PITF, ResourceTemplate(){
456 IRQ(Level,ActiveLow,Exclusive){9}
457 })
459 Device(INTA) {
460 Name(_HID, EISAID("PNP0C0F"))
461 Name(_UID, 1)
463 Method(_STA, 0) {
464 if (PIRA) {
465 Return(0x0B) /* sata is invisible */
466 } else {
467 Return(0x09) /* sata is disabled */
468 }
469 } /* End Method(_SB.INTA._STA) */
471 Method(_DIS ,0) {
472 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
473 Store(0, PIRA)
474 } /* End Method(_SB.INTA._DIS) */
476 Method(_PRS ,0) {
477 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
478 Return(IRQP)
479 } /* Method(_SB.INTA._PRS) */
481 Method(_CRS ,0) {
482 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
483 CreateWordField(IRQB, 0x1, IRQN)
484 ShiftLeft(1, PIRA, IRQN)
485 Return(IRQB)
486 } /* Method(_SB.INTA._CRS) */
488 Method(_SRS, 1) {
489 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
490 CreateWordField(ARG0, 1, IRQM)
492 /* Use lowest available IRQ */
493 FindSetRightBit(IRQM, Local0)
494 if (Local0) {
495 Decrement(Local0)
496 }
497 Store(Local0, PIRA)
498 } /* End Method(_SB.INTA._SRS) */
499 } /* End Device(INTA) */
501 Device(INTB) {
502 Name(_HID, EISAID("PNP0C0F"))
503 Name(_UID, 2)
505 Method(_STA, 0) {
506 if (PIRB) {
507 Return(0x0B) /* sata is invisible */
508 } else {
509 Return(0x09) /* sata is disabled */
510 }
511 } /* End Method(_SB.INTB._STA) */
513 Method(_DIS ,0) {
514 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
515 Store(0, PIRB)
516 } /* End Method(_SB.INTB._DIS) */
518 Method(_PRS ,0) {
519 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
520 Return(IRQP)
521 } /* Method(_SB.INTB._PRS) */
523 Method(_CRS ,0) {
524 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
525 CreateWordField(IRQB, 0x1, IRQN)
526 ShiftLeft(1, PIRB, IRQN)
527 Return(IRQB)
528 } /* Method(_SB.INTB._CRS) */
530 Method(_SRS, 1) {
531 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
532 CreateWordField(ARG0, 1, IRQM)
534 /* Use lowest available IRQ */
535 FindSetRightBit(IRQM, Local0)
536 if (Local0) {
537 Decrement(Local0)
538 }
539 Store(Local0, PIRB)
540 } /* End Method(_SB.INTB._SRS) */
541 } /* End Device(INTB) */
543 Device(INTC) {
544 Name(_HID, EISAID("PNP0C0F"))
545 Name(_UID, 3)
547 Method(_STA, 0) {
548 if (PIRC) {
549 Return(0x0B) /* sata is invisible */
550 } else {
551 Return(0x09) /* sata is disabled */
552 }
553 } /* End Method(_SB.INTC._STA) */
555 Method(_DIS ,0) {
556 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
557 Store(0, PIRC)
558 } /* End Method(_SB.INTC._DIS) */
560 Method(_PRS ,0) {
561 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
562 Return(IRQP)
563 } /* Method(_SB.INTC._PRS) */
565 Method(_CRS ,0) {
566 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
567 CreateWordField(IRQB, 0x1, IRQN)
568 ShiftLeft(1, PIRC, IRQN)
569 Return(IRQB)
570 } /* Method(_SB.INTC._CRS) */
572 Method(_SRS, 1) {
573 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
574 CreateWordField(ARG0, 1, IRQM)
576 /* Use lowest available IRQ */
577 FindSetRightBit(IRQM, Local0)
578 if (Local0) {
579 Decrement(Local0)
580 }
581 Store(Local0, PIRC)
582 } /* End Method(_SB.INTC._SRS) */
583 } /* End Device(INTC) */
585 Device(INTD) {
586 Name(_HID, EISAID("PNP0C0F"))
587 Name(_UID, 4)
589 Method(_STA, 0) {
590 if (PIRD) {
591 Return(0x0B) /* sata is invisible */
592 } else {
593 Return(0x09) /* sata is disabled */
594 }
595 } /* End Method(_SB.INTD._STA) */
597 Method(_DIS ,0) {
598 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
599 Store(0, PIRD)
600 } /* End Method(_SB.INTD._DIS) */
602 Method(_PRS ,0) {
603 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
604 Return(IRQP)
605 } /* Method(_SB.INTD._PRS) */
607 Method(_CRS ,0) {
608 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
609 CreateWordField(IRQB, 0x1, IRQN)
610 ShiftLeft(1, PIRD, IRQN)
611 Return(IRQB)
612 } /* Method(_SB.INTD._CRS) */
614 Method(_SRS, 1) {
615 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
616 CreateWordField(ARG0, 1, IRQM)
618 /* Use lowest available IRQ */
619 FindSetRightBit(IRQM, Local0)
620 if (Local0) {
621 Decrement(Local0)
622 }
623 Store(Local0, PIRD)
624 } /* End Method(_SB.INTD._SRS) */
625 } /* End Device(INTD) */
627 Device(INTE) {
628 Name(_HID, EISAID("PNP0C0F"))
629 Name(_UID, 5)
631 Method(_STA, 0) {
632 if (PIRE) {
633 Return(0x0B) /* sata is invisible */
634 } else {
635 Return(0x09) /* sata is disabled */
636 }
637 } /* End Method(_SB.INTE._STA) */
639 Method(_DIS ,0) {
640 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
641 Store(0, PIRE)
642 } /* End Method(_SB.INTE._DIS) */
644 Method(_PRS ,0) {
645 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
646 Return(IRQP)
647 } /* Method(_SB.INTE._PRS) */
649 Method(_CRS ,0) {
650 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
651 CreateWordField(IRQB, 0x1, IRQN)
652 ShiftLeft(1, PIRE, IRQN)
653 Return(IRQB)
654 } /* Method(_SB.INTE._CRS) */
656 Method(_SRS, 1) {
657 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
658 CreateWordField(ARG0, 1, IRQM)
660 /* Use lowest available IRQ */
661 FindSetRightBit(IRQM, Local0)
662 if (Local0) {
663 Decrement(Local0)
664 }
665 Store(Local0, PIRE)
666 } /* End Method(_SB.INTE._SRS) */
667 } /* End Device(INTE) */
669 Device(INTF) {
670 Name(_HID, EISAID("PNP0C0F"))
671 Name(_UID, 6)
673 Method(_STA, 0) {
674 if (PIRF) {
675 Return(0x0B) /* sata is invisible */
676 } else {
677 Return(0x09) /* sata is disabled */
678 }
679 } /* End Method(_SB.INTF._STA) */
681 Method(_DIS ,0) {
682 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
683 Store(0, PIRF)
684 } /* End Method(_SB.INTF._DIS) */
686 Method(_PRS ,0) {
687 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
688 Return(PITF)
689 } /* Method(_SB.INTF._PRS) */
691 Method(_CRS ,0) {
692 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
693 CreateWordField(IRQB, 0x1, IRQN)
694 ShiftLeft(1, PIRF, IRQN)
695 Return(IRQB)
696 } /* Method(_SB.INTF._CRS) */
698 Method(_SRS, 1) {
699 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
700 CreateWordField(ARG0, 1, IRQM)
702 /* Use lowest available IRQ */
703 FindSetRightBit(IRQM, Local0)
704 if (Local0) {
705 Decrement(Local0)
706 }
707 Store(Local0, PIRF)
708 } /* End Method(_SB.INTF._SRS) */
709 } /* End Device(INTF) */
711 Device(INTG) {
712 Name(_HID, EISAID("PNP0C0F"))
713 Name(_UID, 7)
715 Method(_STA, 0) {
716 if (PIRG) {
717 Return(0x0B) /* sata is invisible */
718 } else {
719 Return(0x09) /* sata is disabled */
720 }
721 } /* End Method(_SB.INTG._STA) */
723 Method(_DIS ,0) {
724 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
725 Store(0, PIRG)
726 } /* End Method(_SB.INTG._DIS) */
728 Method(_PRS ,0) {
729 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
730 Return(IRQP)
731 } /* Method(_SB.INTG._CRS) */
733 Method(_CRS ,0) {
734 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
735 CreateWordField(IRQB, 0x1, IRQN)
736 ShiftLeft(1, PIRG, IRQN)
737 Return(IRQB)
738 } /* Method(_SB.INTG._CRS) */
740 Method(_SRS, 1) {
741 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
742 CreateWordField(ARG0, 1, IRQM)
744 /* Use lowest available IRQ */
745 FindSetRightBit(IRQM, Local0)
746 if (Local0) {
747 Decrement(Local0)
748 }
749 Store(Local0, PIRG)
750 } /* End Method(_SB.INTG._SRS) */
751 } /* End Device(INTG) */
753 Device(INTH) {
754 Name(_HID, EISAID("PNP0C0F"))
755 Name(_UID, 8)
757 Method(_STA, 0) {
758 if (PIRH) {
759 Return(0x0B) /* sata is invisible */
760 } else {
761 Return(0x09) /* sata is disabled */
762 }
763 } /* End Method(_SB.INTH._STA) */
765 Method(_DIS ,0) {
766 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
767 Store(0, PIRH)
768 } /* End Method(_SB.INTH._DIS) */
770 Method(_PRS ,0) {
771 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
772 Return(IRQP)
773 } /* Method(_SB.INTH._CRS) */
775 Method(_CRS ,0) {
776 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
777 CreateWordField(IRQB, 0x1, IRQN)
778 ShiftLeft(1, PIRH, IRQN)
779 Return(IRQB)
780 } /* Method(_SB.INTH._CRS) */
782 Method(_SRS, 1) {
783 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
784 CreateWordField(ARG0, 1, IRQM)
786 /* Use lowest available IRQ */
787 FindSetRightBit(IRQM, Local0)
788 if (Local0) {
789 Decrement(Local0)
790 }
791 Store(Local0, PIRH)
792 } /* End Method(_SB.INTH._SRS) */
793 } /* End Device(INTH) */
795 } /* End Scope(_SB) */
798 /* Supported sleep states: */
799 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
801 If (LAnd(SSFG, 0x01)) {
802 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
803 }
804 If (LAnd(SSFG, 0x02)) {
805 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
806 }
807 If (LAnd(SSFG, 0x04)) {
808 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
809 }
810 If (LAnd(SSFG, 0x08)) {
811 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
812 }
814 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
816 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
817 Name(CSMS, 0) /* Current System State */
819 /* Wake status package */
820 Name(WKST,Package(){Zero, Zero})
822 /*
823 * \_PTS - Prepare to Sleep method
824 *
825 * Entry:
826 * Arg0=The value of the sleeping state S1=1, S2=2, etc
827 *
828 * Exit:
829 * -none-
830 *
831 * The _PTS control method is executed at the beginning of the sleep process
832 * for S1-S5. The sleeping value is passed to the _PTS control method. This
833 * control method may be executed a relatively long time before entering the
834 * sleep state and the OS may abort the operation without notification to
835 * the ACPI driver. This method cannot modify the configuration or power
836 * state of any device in the system.
837 */
838 Method(\_PTS, 1) {
839 /* DBGO("\\_PTS\n") */
840 /* DBGO("From S0 to S") */
841 /* DBGO(Arg0) */
842 /* DBGO("\n") */
844 /* Don't allow PCIRST# to reset USB */
845 if (LEqual(Arg0,3)){
846 Store(0,URRE)
847 }
849 /* Clear sleep SMI status flag and enable sleep SMI trap. */
850 /*Store(One, CSSM)
851 Store(One, SSEN)*/
853 /* On older chips, clear PciExpWakeDisEn */
854 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
855 * Store(0,\_SB.PWDE)
856 *}
857 */
859 /* Clear wake status structure. */
860 Store(0, Index(WKST,0))
861 Store(0, Index(WKST,1))
862 } /* End Method(\_PTS) */
864 /*
865 * The following method results in a "not a valid reserved NameSeg"
866 * warning so I have commented it out for the duration. It isn't
867 * used, so it could be removed.
868 *
869 *
870 * \_GTS OEM Going To Sleep method
871 *
872 * Entry:
873 * Arg0=The value of the sleeping state S1=1, S2=2
874 *
875 * Exit:
876 * -none-
877 *
878 * Method(\_GTS, 1) {
879 * DBGO("\\_GTS\n")
880 * DBGO("From S0 to S")
881 * DBGO(Arg0)
882 * DBGO("\n")
883 * }
884 */
886 /*
887 * \_BFS OEM Back From Sleep method
888 *
889 * Entry:
890 * Arg0=The value of the sleeping state S1=1, S2=2
891 *
892 * Exit:
893 * -none-
894 */
895 Method(\_BFS, 1) {
896 /* DBGO("\\_BFS\n") */
897 /* DBGO("From S") */
898 /* DBGO(Arg0) */
899 /* DBGO(" to S0\n") */
900 }
902 /*
903 * \_WAK System Wake method
904 *
905 * Entry:
906 * Arg0=The value of the sleeping state S1=1, S2=2
907 *
908 * Exit:
909 * Return package of 2 DWords
910 * Dword 1 - Status
911 * 0x00000000 wake succeeded
912 * 0x00000001 Wake was signaled but failed due to lack of power
913 * 0x00000002 Wake was signaled but failed due to thermal condition
914 * Dword 2 - Power Supply state
915 * if non-zero the effective S-state the power supply entered
916 */
917 Method(\_WAK, 1) {
918 /* DBGO("\\_WAK\n") */
919 /* DBGO("From S") */
920 /* DBGO(Arg0) */
921 /* DBGO(" to S0\n") */
923 /* Re-enable HPET */
924 Store(1,HPDE)
926 /* Restore PCIRST# so it resets USB */
927 if (LEqual(Arg0,3)){
928 Store(1,URRE)
929 }
931 /* Arbitrarily clear PciExpWakeStatus */
932 Store(PWST, PWST)
934 /* if(DeRefOf(Index(WKST,0))) {
935 * Store(0, Index(WKST,1))
936 * } else {
937 * Store(Arg0, Index(WKST,1))
938 * }
939 */
940 Return(WKST)
941 } /* End Method(\_WAK) */
943 Scope(\_GPE) { /* Start Scope GPE */
944 /* General event 0 */
945 /* Method(_L00) {
946 * DBGO("\\_GPE\\_L00\n")
947 * }
948 */
950 /* General event 1 */
951 /* Method(_L01) {
952 * DBGO("\\_GPE\\_L00\n")
953 * }
954 */
956 /* General event 2 */
957 /* Method(_L02) {
958 * DBGO("\\_GPE\\_L00\n")
959 * }
960 */
962 /* General event 3 */
963 Method(_L03) {
964 /* DBGO("\\_GPE\\_L00\n") */
965 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
966 }
968 /* General event 4 */
969 /* Method(_L04) {
970 * DBGO("\\_GPE\\_L00\n")
971 * }
972 */
974 /* General event 5 */
975 /* Method(_L05) {
976 * DBGO("\\_GPE\\_L00\n")
977 * }
978 */
980 /* General event 6 - Used for GPM6, moved to USB.asl */
981 /* Method(_L06) {
982 * DBGO("\\_GPE\\_L00\n")
983 * }
984 */
986 /* General event 7 - Used for GPM7, moved to USB.asl */
987 /* Method(_L07) {
988 * DBGO("\\_GPE\\_L07\n")
989 * }
990 */
992 /* Legacy PM event */
993 Method(_L08) {
994 /* DBGO("\\_GPE\\_L08\n") */
995 }
997 /* Temp warning (TWarn) event */
998 Method(_L09) {
999 /* DBGO("\\_GPE\\_L09\n") */
1000 /* Notify (\_TZ.TZ00, 0x80) */
1001 }
1003 /* Reserved */
1004 /* Method(_L0A) {
1005 * DBGO("\\_GPE\\_L0A\n")
1006 * }
1007 */
1009 /* USB controller PME# */
1010 Method(_L0B) {
1011 /* DBGO("\\_GPE\\_L0B\n") */
1012 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1013 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1014 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1015 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1016 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1017 Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
1018 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1019 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1020 }
1022 /* AC97 controller PME# */
1023 /* Method(_L0C) {
1024 * DBGO("\\_GPE\\_L0C\n")
1025 * }
1026 */
1028 /* OtherTherm PME# */
1029 /* Method(_L0D) {
1030 * DBGO("\\_GPE\\_L0D\n")
1031 * }
1032 */
1034 /* GPM9 SCI event - Moved to USB.asl */
1035 /* Method(_L0E) {
1036 * DBGO("\\_GPE\\_L0E\n")
1037 * }
1038 */
1040 /* PCIe HotPlug event */
1041 /* Method(_L0F) {
1042 * DBGO("\\_GPE\\_L0F\n")
1043 * }
1044 */
1046 /* ExtEvent0 SCI event */
1047 Method(_L10) {
1048 /* DBGO("\\_GPE\\_L10\n") */
1049 }
1052 /* ExtEvent1 SCI event */
1053 Method(_L11) {
1054 /* DBGO("\\_GPE\\_L11\n") */
1055 }
1057 /* PCIe PME# event */
1058 /* Method(_L12) {
1059 * DBGO("\\_GPE\\_L12\n")
1060 * }
1061 */
1063 /* GPM0 SCI event - Moved to USB.asl */
1064 /* Method(_L13) {
1065 * DBGO("\\_GPE\\_L13\n")
1066 * }
1067 */
1069 /* GPM1 SCI event - Moved to USB.asl */
1070 /* Method(_L14) {
1071 * DBGO("\\_GPE\\_L14\n")
1072 * }
1073 */
1075 /* GPM2 SCI event - Moved to USB.asl */
1076 /* Method(_L15) {
1077 * DBGO("\\_GPE\\_L15\n")
1078 * }
1079 */
1081 /* GPM3 SCI event - Moved to USB.asl */
1082 /* Method(_L16) {
1083 * DBGO("\\_GPE\\_L16\n")
1084 * }
1085 */
1087 /* GPM8 SCI event - Moved to USB.asl */
1088 /* Method(_L17) {
1089 * DBGO("\\_GPE\\_L17\n")
1090 * }
1091 */
1093 /* GPIO0 or GEvent8 event */
1094 Method(_L18) {
1095 /* DBGO("\\_GPE\\_L18\n") */
1096 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1097 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1098 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1099 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1100 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1101 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1102 }
1104 /* GPM4 SCI event - Moved to USB.asl */
1105 /* Method(_L19) {
1106 * DBGO("\\_GPE\\_L19\n")
1107 * }
1108 */
1110 /* GPM5 SCI event - Moved to USB.asl */
1111 /* Method(_L1A) {
1112 * DBGO("\\_GPE\\_L1A\n")
1113 * }
1114 */
1116 /* Azalia SCI event */
1117 Method(_L1B) {
1118 /* DBGO("\\_GPE\\_L1B\n") */
1119 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1120 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1121 }
1123 /* GPM6 SCI event - Reassigned to _L06 */
1124 /* Method(_L1C) {
1125 * DBGO("\\_GPE\\_L1C\n")
1126 * }
1127 */
1129 /* GPM7 SCI event - Reassigned to _L07 */
1130 /* Method(_L1D) {
1131 * DBGO("\\_GPE\\_L1D\n")
1132 * }
1133 */
1135 /* GPIO2 or GPIO66 SCI event */
1136 /* Method(_L1E) {
1137 * DBGO("\\_GPE\\_L1E\n")
1138 * }
1139 */
1141 /* SATA SCI event - Moved to sata.asl */
1142 /* Method(_L1F) {
1143 * DBGO("\\_GPE\\_L1F\n")
1144 * }
1145 */
1147 } /* End Scope GPE */
1149 #include "acpi/usb.asl"
1151 /* South Bridge */
1152 Scope(\_SB) { /* Start \_SB scope */
1153 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1155 /* _SB.PCI0 */
1156 /* Note: Only need HID on Primary Bus */
1157 Device(PCI0) {
1158 External (TOM1)
1159 External (TOM2)
1160 Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
1161 Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
1162 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1164 /* Operating System Capabilities Method */
1165 Method(_OSC,4)
1166 { /* Check for proper PCI/PCIe UUID */
1167 If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
1168 {
1169 /* Let OS control everything */
1170 Return (Arg3)
1171 }
1172 }
1174 Method(_BBN, 0) { /* Bus number = 0 */
1175 Return(0)
1176 }
1177 Method(_STA, 0) {
1178 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1179 Return(0x0B) /* Status is visible */
1180 }
1182 Method(_PRT,0) {
1183 If(PMOD){ Return(APR0) } /* APIC mode */
1184 Return (PR0) /* PIC Mode */
1185 } /* end _PRT */
1187 /* Describe the Northbridge devices */
1188 Device(AMRT) {
1189 Name(_ADR, 0x00000000)
1190 } /* end AMRT */
1192 /* The internal GFX bridge */
1193 Device(AGPB) {
1194 Name(_ADR, 0x00010000)
1195 Name(_PRW, Package() {0x18, 4})
1196 Method(_PRT,0) {
1197 Return (APR1)
1198 }
1199 } /* end AGPB */
1201 /* The external GFX bridge */
1202 Device(PBR2) {
1203 Name(_ADR, 0x00020000)
1204 Name(_PRW, Package() {0x18, 4})
1205 Method(_PRT,0) {
1206 If(PMOD){ Return(APS2) } /* APIC mode */
1207 Return (PS2) /* PIC Mode */
1208 } /* end _PRT */
1209 } /* end PBR2 */
1211 /* Dev3 is also an external GFX bridge, not used in Herring */
1213 Device(PBR4) {
1214 Name(_ADR, 0x00040000)
1215 Name(_PRW, Package() {0x18, 4})
1216 Method(_PRT,0) {
1217 If(PMOD){ Return(APS4) } /* APIC mode */
1218 Return (PS4) /* PIC Mode */
1219 } /* end _PRT */
1220 } /* end PBR4 */
1222 Device(PBR5) {
1223 Name(_ADR, 0x00050000)
1224 Name(_PRW, Package() {0x18, 4})
1225 Method(_PRT,0) {
1226 If(PMOD){ Return(APS5) } /* APIC mode */
1227 Return (PS5) /* PIC Mode */
1228 } /* end _PRT */
1229 } /* end PBR5 */
1231 Device(PBR6) {
1232 Name(_ADR, 0x00060000)
1233 Name(_PRW, Package() {0x18, 4})
1234 Method(_PRT,0) {
1235 If(PMOD){ Return(APS6) } /* APIC mode */
1236 Return (PS6) /* PIC Mode */
1237 } /* end _PRT */
1238 } /* end PBR6 */
1240 /* The onboard EtherNet chip */
1241 Device(PBR7) {
1242 Name(_ADR, 0x00070000)
1243 Name(_PRW, Package() {0x18, 4})
1244 Method(_PRT,0) {
1245 If(PMOD){ Return(APS7) } /* APIC mode */
1246 Return (PS7) /* PIC Mode */
1247 } /* end _PRT */
1248 } /* end PBR7 */
1250 /* GPP */
1251 Device(PBR9) {
1252 Name(_ADR, 0x00090000)
1253 Name(_PRW, Package() {0x18, 4})
1254 Method(_PRT,0) {
1255 If(PMOD){ Return(APS9) } /* APIC mode */
1256 Return (PS9) /* PIC Mode */
1257 } /* end _PRT */
1258 } /* end PBR9 */
1260 Device(PBRa) {
1261 Name(_ADR, 0x000A0000)
1262 Name(_PRW, Package() {0x18, 4})
1263 Method(_PRT,0) {
1264 If(PMOD){ Return(APSa) } /* APIC mode */
1265 Return (PSa) /* PIC Mode */
1266 } /* end _PRT */
1267 } /* end PBRa */
1269 Device(PE20) {
1270 Name(_ADR, 0x00150000)
1271 Name(_PRW, Package() {0x18, 4})
1272 Method(_PRT,0) {
1273 If(PMOD){ Return(APE0) } /* APIC mode */
1274 Return (PE0) /* PIC Mode */
1275 } /* end _PRT */
1276 } /* end PE20 */
1277 Device(PE21) {
1278 Name(_ADR, 0x00150001)
1279 Name(_PRW, Package() {0x18, 4})
1280 Method(_PRT,0) {
1281 If(PMOD){ Return(APE1) } /* APIC mode */
1282 Return (PE1) /* PIC Mode */
1283 } /* end _PRT */
1284 } /* end PE21 */
1285 Device(PE22) {
1286 Name(_ADR, 0x00150002)
1287 Name(_PRW, Package() {0x18, 4})
1288 Method(_PRT,0) {
1289 If(PMOD){ Return(APE2) } /* APIC mode */
1290 Return (APE2) /* PIC Mode */
1291 } /* end _PRT */
1292 } /* end PE22 */
1293 Device(PE23) {
1294 Name(_ADR, 0x00150003)
1295 Name(_PRW, Package() {0x18, 4})
1296 Method(_PRT,0) {
1297 If(PMOD){ Return(APE3) } /* APIC mode */
1298 Return (PE3) /* PIC Mode */
1299 } /* end _PRT */
1300 } /* end PE23 */
1302 /* PCI slot 1, 2, 3 */
1303 Device(PIBR) {
1304 Name(_ADR, 0x00140004)
1305 Name(_PRW, Package() {0x18, 4})
1307 Method(_PRT, 0) {
1308 Return (PCIB)
1309 }
1310 }
1312 /* Describe the Southbridge devices */
1313 Device(STCR) {
1314 Name(_ADR, 0x00110000)
1315 #include "acpi/sata.asl"
1316 } /* end STCR */
1318 Device(UOH1) {
1319 Name(_ADR, 0x00120000)
1320 Name(_PRW, Package() {0x0B, 3})
1321 } /* end UOH1 */
1323 Device(UOH2) {
1324 Name(_ADR, 0x00120002)
1325 Name(_PRW, Package() {0x0B, 3})
1326 } /* end UOH2 */
1328 Device(UOH3) {
1329 Name(_ADR, 0x00130000)
1330 Name(_PRW, Package() {0x0B, 3})
1331 } /* end UOH3 */
1333 Device(UOH4) {
1334 Name(_ADR, 0x00130002)
1335 Name(_PRW, Package() {0x0B, 3})
1336 } /* end UOH4 */
1338 Device(UOH5) {
1339 Name(_ADR, 0x00160000)
1340 Name(_PRW, Package() {0x0B, 3})
1341 } /* end UOH5 */
1343 Device(UOH6) {
1344 Name(_ADR, 0x00160002)
1345 Name(_PRW, Package() {0x0B, 3})
1346 } /* end UOH5 */
1348 Device(UEH1) {
1349 Name(_ADR, 0x00140005)
1350 Name(_PRW, Package() {0x0B, 3})
1351 } /* end UEH1 */
1353 Device(SBUS) {
1354 Name(_ADR, 0x00140000)
1355 } /* end SBUS */
1357 /* Primary (and only) IDE channel */
1358 Device(IDEC) {
1359 Name(_ADR, 0x00140001)
1360 #include "acpi/ide.asl"
1361 } /* end IDEC */
1363 Device(AZHD) {
1364 Name(_ADR, 0x00140002)
1365 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1366 Field(AZPD, AnyAcc, NoLock, Preserve) {
1367 offset (0x42),
1368 NSDI, 1,
1369 NSDO, 1,
1370 NSEN, 1,
1371 offset (0x44),
1372 IPCR, 4,
1373 offset (0x54),
1374 PWST, 2,
1375 , 6,
1376 PMEB, 1,
1377 , 6,
1378 PMST, 1,
1379 offset (0x62),
1380 MMCR, 1,
1381 offset (0x64),
1382 MMLA, 32,
1383 offset (0x68),
1384 MMHA, 32,
1385 offset (0x6C),
1386 MMDT, 16,
1387 }
1388 } /* end AZHD */
1390 Device(LIBR) {
1391 Name(_ADR, 0x00140003)
1392 /* Method(_INI) {
1393 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1394 } */ /* End Method(_SB.SBRDG._INI) */
1396 /* Real Time Clock Device */
1397 Device(RTC0) {
1398 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1399 Name(_CRS, ResourceTemplate() {
1400 IRQNoFlags(){8}
1401 IO(Decode16,0x0070, 0x0070, 0, 2)
1402 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1403 })
1404 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1406 Device(TMR) { /* Timer */
1407 Name(_HID,EISAID("PNP0100")) /* System Timer */
1408 Name(_CRS, ResourceTemplate() {
1409 IRQNoFlags(){0}
1410 IO(Decode16, 0x0040, 0x0040, 0, 4)
1411 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1412 })
1413 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1415 Device(SPKR) { /* Speaker */
1416 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1417 Name(_CRS, ResourceTemplate() {
1418 IO(Decode16, 0x0061, 0x0061, 0, 1)
1419 })
1420 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1422 Device(PIC) {
1423 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1424 Name(_CRS, ResourceTemplate() {
1425 IRQNoFlags(){2}
1426 IO(Decode16,0x0020, 0x0020, 0, 2)
1427 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1428 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1429 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1430 })
1431 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1433 Device(MAD) { /* 8257 DMA */
1434 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1435 Name(_CRS, ResourceTemplate() {
1436 DMA(Compatibility,BusMaster,Transfer8){4}
1437 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1438 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1439 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1440 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1441 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1442 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1443 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1444 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1446 Device(COPR) {
1447 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1448 Name(_CRS, ResourceTemplate() {
1449 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1450 IRQNoFlags(){13}
1451 })
1452 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1453 #if 0
1454 Device(HPTM) {
1455 Name(_HID,EISAID("PNP0103"))
1456 Name(CRS,ResourceTemplate() {
1457 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1458 })
1459 Method(_STA, 0) {
1460 Return(0x0F) /* sata is visible */
1461 }
1462 Method(_CRS, 0) {
1463 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1464 Store(HPBA, HPBA)
1465 Return(CRS)
1466 }
1467 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1468 #endif
1469 } /* end LIBR */
1471 Device(HPBR) {
1472 Name(_ADR, 0x00140004)
1473 } /* end HostPciBr */
1475 Device(ACAD) {
1476 Name(_ADR, 0x00140005)
1477 } /* end Ac97audio */
1479 Device(ACMD) {
1480 Name(_ADR, 0x00140006)
1481 } /* end Ac97modem */
1483 Name(CRES, ResourceTemplate() {
1484 /* Set the Bus number and Secondary Bus number for the PCI0 device
1485 * The Secondary bus range for PCI0 lets the system
1486 * know what bus values are allowed on the downstream
1487 * side of this PCI bus if there is a PCI-PCI bridge.
1488 * PCI busses can have 256 secondary busses which
1489 * range from [0-0xFF] but they do not need to be
1490 * sequential.
1491 */
1492 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
1493 0x0000, /* address granularity */
1494 0x0000, /* range minimum */
1495 0x00FF, /* range maximum */
1496 0x0000, /* translation */
1497 0x0100, /* length */
1498 ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
1500 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1502 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1503 0x0000, /* address granularity */
1504 0x0000, /* range minimum */
1505 0x0CF7, /* range maximum */
1506 0x0000, /* translation */
1507 0x0CF8 /* length */
1508 )
1510 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1511 0x0000, /* address granularity */
1512 0x0D00, /* range minimum */
1513 0xFFFF, /* range maximum */
1514 0x0000, /* translation */
1515 0xF300 /* length */
1516 )
1518 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1519 #if 0
1520 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1521 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1523 /* DRAM Memory from 1MB to TopMem */
1524 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1526 /* BIOS space just below 4GB */
1527 DWORDMemory(
1528 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1529 0x00, /* Granularity */
1530 0x00000000, /* Min */
1531 0x00000000, /* Max */
1532 0x00000000, /* Translation */
1533 0x00000001, /* Max-Min, RLEN */
1534 ,,
1535 PCBM
1536 )
1538 /* DRAM memory from 4GB to TopMem2 */
1539 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1540 0x00000000, /* Granularity */
1541 0x00000000, /* Min */
1542 0x00000000, /* Max */
1543 0x00000000, /* Translation */
1544 0x00000001, /* Max-Min, RLEN */
1545 ,,
1546 DMHI
1547 )
1549 /* BIOS space just below 16EB */
1550 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1551 0x00000000, /* Granularity */
1552 0x00000000, /* Min */
1553 0x00000000, /* Max */
1554 0x00000000, /* Translation */
1555 0x00000001, /* Max-Min, RLEN */
1556 ,,
1557 PEBM
1558 )
1559 #endif
1560 /* memory space for PCI BARs below 4GB */
1561 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1562 }) /* End Name(_SB.PCI0.CRES) */
1564 Method(_CRS, 0) {
1565 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1566 #if 0
1567 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1568 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1569 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1570 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1571 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1572 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1574 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1575 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1576 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1577 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1579 If(LGreater(LOMH, 0xC0000)){
1580 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1581 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1582 }
1584 /* Set size of memory from 1MB to TopMem */
1585 Subtract(TOM1, 0x100000, DMLL)
1587 /*
1588 * If(LNotEqual(TOM2, 0x00000000)){
1589 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1590 * Subtract(TOM2, 0x100000000, DMHL)
1591 * }
1592 */
1594 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1595 If(LEqual(TOM2, 0x00000000)){
1596 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1597 Store(PBLN,PBML)
1598 }
1599 Else { /* Otherwise, put the BIOS just below 16EB */
1600 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1601 Store(PBLN,EBML)
1602 }
1603 #endif
1604 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1605 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1606 /*
1607 * Declare memory between TOM1 and 4GB as available
1608 * for PCI MMIO.
1609 * Use ShiftLeft to avoid 64bit constant (for XP).
1610 * This will work even if the OS does 32bit arithmetic, as
1611 * 32bit (0x00000000 - TOM1) will wrap and give the same
1612 * result as 64bit (0x100000000 - TOM1).
1613 */
1614 Store(TOM1, MM1B)
1615 ShiftLeft(0x10000000, 4, Local0)
1616 Subtract(Local0, TOM1, Local0)
1617 Store(Local0, MM1L)
1619 Return(CRES) /* note to change the Name buffer */
1620 } /* end of Method(_SB.PCI0._CRS) */
1622 /*
1623 *
1624 * FIRST METHOD CALLED UPON BOOT
1625 *
1626 * 1. If debugging, print current OS and ACPI interpreter.
1627 * 2. Get PCI Interrupt routing from ACPI VSM, this
1628 * value is based on user choice in BIOS setup.
1629 */
1630 Method(_INI, 0) {
1631 /* DBGO("\\_SB\\_INI\n") */
1632 /* DBGO(" DSDT.ASL code from ") */
1633 /* DBGO(__DATE__) */
1634 /* DBGO(" ") */
1635 /* DBGO(__TIME__) */
1636 /* DBGO("\n Sleep states supported: ") */
1637 /* DBGO("\n") */
1638 /* DBGO(" \\_OS=") */
1639 /* DBGO(\_OS) */
1640 /* DBGO("\n \\_REV=") */
1641 /* DBGO(\_REV) */
1642 /* DBGO("\n") */
1644 /* Determine the OS we're running on */
1645 CkOT()
1647 /* On older chips, clear PciExpWakeDisEn */
1648 /*if (LLessEqual(\SBRI, 0x13)) {
1649 * Store(0,\PWDE)
1650 * }
1651 */
1652 } /* End Method(_SB._INI) */
1653 } /* End Device(PCI0) */
1655 Device(PWRB) { /* Start Power button device */
1656 Name(_HID, EISAID("PNP0C0C"))
1657 Name(_UID, 0xAA)
1658 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1659 Name(_STA, 0x0B) /* sata is invisible */
1660 }
1661 } /* End \_SB scope */
1663 Scope(\_SI) {
1664 Method(_SST, 1) {
1665 /* DBGO("\\_SI\\_SST\n") */
1666 /* DBGO(" New Indicator state: ") */
1667 /* DBGO(Arg0) */
1668 /* DBGO("\n") */
1669 }
1670 } /* End Scope SI */
1671 #if 0
1672 /* SMBUS Support */
1673 Mutex (SBX0, 0x00)
1674 OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1675 Field (SMB0, ByteAcc, NoLock, Preserve) {
1676 HSTS, 8, /* SMBUS status */
1677 SSTS, 8, /* SMBUS slave status */
1678 HCNT, 8, /* SMBUS control */
1679 HCMD, 8, /* SMBUS host cmd */
1680 HADD, 8, /* SMBUS address */
1681 DAT0, 8, /* SMBUS data0 */
1682 DAT1, 8, /* SMBUS data1 */
1683 BLKD, 8, /* SMBUS block data */
1684 SCNT, 8, /* SMBUS slave control */
1685 SCMD, 8, /* SMBUS shaow cmd */
1686 SEVT, 8, /* SMBUS slave event */
1687 SDAT, 8 /* SMBUS slave data */
1688 }
1690 Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1691 Store (0x1E, HSTS)
1692 Store (0xFA, Local0)
1693 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1694 Stall (0x64)
1695 Decrement (Local0)
1696 }
1698 Return (Local0)
1699 }
1701 Method (SWTC, 1, NotSerialized) {
1702 Store (Arg0, Local0)
1703 Store (0x07, Local2)
1704 Store (One, Local1)
1705 While (LEqual (Local1, One)) {
1706 Store (And (HSTS, 0x1E), Local3)
1707 If (LNotEqual (Local3, Zero)) { /* read sucess */
1708 If (LEqual (Local3, 0x02)) {
1709 Store (Zero, Local2)
1710 }
1712 Store (Zero, Local1)
1713 }
1714 Else {
1715 If (LLess (Local0, 0x0A)) { /* read failure */
1716 Store (0x10, Local2)
1717 Store (Zero, Local1)
1718 }
1719 Else {
1720 Sleep (0x0A) /* 10 ms, try again */
1721 Subtract (Local0, 0x0A, Local0)
1722 }
1723 }
1724 }
1726 Return (Local2)
1727 }
1729 Method (SMBR, 3, NotSerialized) {
1730 Store (0x07, Local0)
1731 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1732 Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1733 If (LEqual (Local0, Zero)) {
1734 Release (SBX0)
1735 Return (0x0)
1736 }
1738 Store (0x1F, HSTS)
1739 Store (Or (ShiftLeft (Arg1, One), One), HADD)
1740 Store (Arg2, HCMD)
1741 If (LEqual (Arg0, 0x07)) {
1742 Store (0x48, HCNT) /* read byte */
1743 }
1745 Store (SWTC (0x03E8), Local1) /* 1000 ms */
1746 If (LEqual (Local1, Zero)) {
1747 If (LEqual (Arg0, 0x07)) {
1748 Store (DAT0, Local0)
1749 }
1750 }
1751 Else {
1752 Store (Local1, Local0)
1753 }
1755 Release (SBX0)
1756 }
1758 /* DBGO("the value of SMBusData0 register ") */
1759 /* DBGO(Arg2) */
1760 /* DBGO(" is ") */
1761 /* DBGO(Local0) */
1762 /* DBGO("\n") */
1764 Return (Local0)
1765 }
1767 /* THERMAL */
1768 Scope(\_TZ) {
1769 Name (KELV, 2732)
1770 Name (THOT, 800)
1771 Name (TCRT, 850)
1773 ThermalZone(TZ00) {
1774 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1775 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1776 Return(Add(0, 2730))
1777 }
1778 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1779 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1780 Return(Package() {\_TZ.TZ00.FAN0})
1781 }
1782 Device (FAN0) {
1783 Name(_HID, EISAID("PNP0C0B"))
1784 Name(_PR0, Package() {PFN0})
1785 }
1787 PowerResource(PFN0,0,0) {
1788 Method(_STA) {
1789 Store(0xF,Local0)
1790 Return(Local0)
1791 }
1792 Method(_ON) {
1793 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1794 }
1795 Method(_OFF) {
1796 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1797 }
1798 }
1800 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1801 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1802 Return (Add (THOT, KELV))
1803 }
1804 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1805 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1806 Return (Add (TCRT, KELV))
1807 }
1808 Method(_TMP,0) { /* return current temp of this zone */
1809 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1810 If (LGreater (Local0, 0x10)) {
1811 Store (Local0, Local1)
1812 }
1813 Else {
1814 Add (Local0, THOT, Local0)
1815 Return (Add (400, KELV))
1816 }
1818 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1819 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1820 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1821 If (LGreater (Local0, 0x10)) {
1822 If (LGreater (Local0, Local1)) {
1823 Store (Local0, Local1)
1824 }
1826 Multiply (Local1, 10, Local1)
1827 Return (Add (Local1, KELV))
1828 }
1829 Else {
1830 Add (Local0, THOT, Local0)
1831 Return (Add (400 , KELV))
1832 }
1833 } /* end of _TMP */
1834 } /* end of TZ00 */
1835 }
1836 #endif
1837 }
1838 /* End of ASL file */