src/soc/intel/jasperlake/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _SOC_CHIP_H_
   4 #define _SOC_CHIP_H_
   5
   6 #include <drivers/i2c/designware/dw_i2c.h>
   7 #include <intelblocks/cfg.h>
   8 #include <intelblocks/gpio.h>
   9 #include <intelblocks/gspi.h>
  10 #include <intelblocks/power_limit.h>
  11 #include <soc/gpe.h>
  12 #include <soc/pch.h>
  13 #include <soc/pci_devs.h>
  14 #include <soc/pmc.h>
  15 #include <soc/serialio.h>
  16 #include <soc/usb.h>
  17 #include <stdint.h>
  18
  19 #define MAX_HD_AUDIO_DMIC_LINKS 2
  20 #define MAX_HD_AUDIO_SNDW_LINKS 4
  21 #define MAX_HD_AUDIO_SSP_LINKS  6
  22
  23 struct soc_intel_jasperlake_config {
  24
  25         /* Common struct containing soc config data required by common code */
  26         struct soc_intel_common_config common_soc_config;
  27
  28         /* Common struct containing power limits configuration information */
  29         struct soc_power_limits_config power_limits_config;
  30
  31         /* Gpio group routed to each dword of the GPE0 block. Values are
  32          * of the form PMC_GPP_[A:U] or GPD. */
  33         uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
  34         uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
  35         uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
  36
  37         /* Generic IO decode ranges */
  38         uint32_t gen1_dec;
  39         uint32_t gen2_dec;
  40         uint32_t gen3_dec;
  41         uint32_t gen4_dec;
  42
  43         /* Enable S0iX support */
  44         int s0ix_enable;
  45         /* Enable DPTF support */
  46         int dptf_enable;
  47
  48         /* Deep SX enable for both AC and DC */
  49         int deep_s3_enable_ac;
  50         int deep_s3_enable_dc;
  51         int deep_s5_enable_ac;
  52         int deep_s5_enable_dc;
  53
  54         /* Deep Sx Configuration
  55          *  DSX_EN_WAKE_PIN       - Enable WAKE# pin
  56          *  DSX_EN_LAN_WAKE_PIN   - Enable LAN_WAKE# pin
  57          *  DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
  58         uint32_t deep_sx_config;
  59
  60         /* TCC activation offset */
  61         uint32_t tcc_offset;
  62
  63         /* System Agent dynamic frequency support.
  64          * When enabled memory will be training at different frequencies.
  65          * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2
  66          * (high), 4:Enabled */
  67         enum {
  68                 SaGv_Disabled,
  69                 SaGv_FixedPoint0,
  70                 SaGv_FixedPoint1,
  71                 SaGv_FixedPoint2,
  72                 SaGv_Enabled,
  73         } SaGv;
  74
  75         /* Rank Margin Tool. 1:Enable, 0:Disable */
  76         uint8_t RMT;
  77
  78         /* USB related */
  79         struct usb2_port_config usb2_ports[16];
  80         struct usb3_port_config usb3_ports[10];
  81         /* Wake Enable Bitmap for USB2 ports */
  82         uint16_t usb2_wake_enable_bitmap;
  83         /* Wake Enable Bitmap for USB3 ports */
  84         uint16_t usb3_wake_enable_bitmap;
  85
  86         /* SATA related */
  87         uint8_t SataMode;
  88         uint8_t SataSalpSupport;
  89         uint8_t SataPortsEnable[8];
  90         uint8_t SataPortsDevSlp[8];
  91
  92         /* Audio related */
  93         uint8_t PchHdaDspEnable;
  94         uint8_t PchHdaAudioLinkHdaEnable;
  95         uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
  96         uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
  97         uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
  98         uint8_t PchHdaIDispLinkTmode;
  99         uint8_t PchHdaIDispLinkFrequency;
 100         uint8_t PchHdaIDispCodecDisconnect;
 101
 102         /* PCIe Root Ports */
 103         uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
 104         /* PCIe output clocks type to PCIe devices.
 105          * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 106          * 0xFF: not used */
 107         uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
 108         /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
 109          * clksrc. */
 110         uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
 111
 112         /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
 113         uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
 114
 115         /* PCIe RP L1 substate */
 116         enum L1_substates_control {
 117                 L1_SS_FSP_DEFAULT,
 118                 L1_SS_DISABLED,
 119                 L1_SS_L1_1,
 120                 L1_SS_L1_2,
 121         } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 122
 123         /* SMBus */
 124         uint8_t SmbusEnable;
 125
 126         /* eMMC and SD */
 127         uint8_t ScsEmmcHs400Enabled;
 128
 129         /* Enable if SD Card Power Enable Signal is Active High */
 130         uint8_t SdCardPowerEnableActiveHigh;
 131
 132         /* Integrated Sensor */
 133         uint8_t PchIshEnable;
 134
 135         /* Heci related */
 136         uint8_t Heci3Enabled;
 137
 138         /* VR Config Settings for IA Core */
 139         uint16_t ImonSlope;
 140         uint16_t ImonOffset;
 141
 142         /* Gfx related */
 143         uint8_t IgdDvmt50PreAlloc;
 144         uint8_t SkipExtGfxScan;
 145
 146         uint32_t GraphicsConfigPtr;
 147
 148         /* HeciEnabled decides the state of Heci1 at end of boot
 149          * Setting to 0 (default) disables Heci1 and hides the device from OS */
 150         uint8_t HeciEnabled;
 151
 152         /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
 153         uint8_t eist_enable;
 154
 155         /* Enable C6 DRAM */
 156         uint8_t enable_c6dram;
 157         /*
 158          * PRMRR size setting with below options
 159          * Disable: 0x0
 160          * 32MB: 0x2000000
 161          * 64MB: 0x4000000
 162          * 128 MB: 0x8000000
 163          * 256 MB: 0x10000000
 164          * 512 MB: 0x20000000
 165          */
 166         uint32_t PrmrrSize;
 167         uint8_t PmTimerDisabled;
 168         /*
 169          * SerialIO device mode selection:
 170          * PchSerialIoDisabled,
 171          * PchSerialIoPci,
 172          * PchSerialIoHidden,
 173          * PchSerialIoLegacyUart,
 174          * PchSerialIoSkipInit
 175          */
 176         uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
 177         uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 178         uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
 179         /*
 180          * GSPIn Default Chip Select Mode:
 181          * 0:Hardware Mode,
 182          * 1:Software Mode
 183          */
 184         uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 185         /*
 186          * GSPIn Default Chip Select State:
 187          * 0: Low,
 188          * 1: High
 189          */
 190         uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 191
 192         /*
 193          * TraceHubMode config
 194          * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
 195          */
 196         uint8_t TraceHubMode;
 197
 198         /* Debug interface selection */
 199         enum {
 200                 DEBUG_INTERFACE_RAM = (1 << 0),
 201                 DEBUG_INTERFACE_UART_8250IO = (1 << 1),
 202                 DEBUG_INTERFACE_USB3 = (1 << 3),
 203                 DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4),
 204                 DEBUG_INTERFACE_TRACEHUB = (1 << 5),
 205         } debug_interface_flag;
 206
 207         /* GPIO SD card detect pin */
 208         unsigned int sdcard_cd_gpio;
 209
 210         /* Enable Pch iSCLK */
 211         uint8_t pch_isclk;
 212
 213         /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
 214         enum {
 215                 FORCE_DISABLE,
 216                 FORCE_ENABLE,
 217         } CnviBtAudioOffload;
 218
 219         /* Tcss */
 220         uint8_t TcssXhciEn;
 221         uint8_t TcssXdciEn;
 222
 223         /*
 224          * Override GPIO PM configuration:
 225          * 0: Use FSP default GPIO PM program,
 226          * 1: coreboot to override GPIO PM program
 227          */
 228         uint8_t gpio_override_pm;
 229
 230         /*
 231          * GPIO PM configuration: 0 to disable, 1 to enable power gating
 232          * Bit 6-7: Reserved
 233          * Bit 5: MISCCFG_GPSIDEDPCGEN
 234          * Bit 4: MISCCFG_GPRCOMPCDLCGEN
 235          * Bit 3: MISCCFG_GPRTCDLCGEN
 236          * Bit 2: MISCCFG_GSXLCGEN
 237          * Bit 1: MISCCFG_GPDPCGEN
 238          * Bit 0: MISCCFG_GPDLCGEN
 239          */
 240         uint8_t gpio_pm[TOTAL_GPIO_COMM];
 241
 242         /* DP config */
 243         /*
 244          * Port config
 245          * 0:Disabled, 1:eDP, 2:MIPI DSI
 246          */
 247         uint8_t DdiPortAConfig;
 248         uint8_t DdiPortBConfig;
 249
 250         /* Enable(1)/Disable(0) HPD */
 251         uint8_t DdiPortAHpd;
 252         uint8_t DdiPortBHpd;
 253         uint8_t DdiPortCHpd;
 254         uint8_t DdiPort1Hpd;
 255         uint8_t DdiPort2Hpd;
 256         uint8_t DdiPort3Hpd;
 257         uint8_t DdiPort4Hpd;
 258
 259         /* Enable(1)/Disable(0) DDC */
 260         uint8_t DdiPortADdc;
 261         uint8_t DdiPortBDdc;
 262         uint8_t DdiPortCDdc;
 263         uint8_t DdiPort1Ddc;
 264         uint8_t DdiPort2Ddc;
 265         uint8_t DdiPort3Ddc;
 266         uint8_t DdiPort4Ddc;
 267
 268         /* Hybrid storage mode enable (1) / disable (0)
 269          * This mode makes FSP detect Optane and NVME and set PCIe lane mode
 270          * accordingly */
 271         uint8_t HybridStorageMode;
 272
 273         /*
 274          * Override CPU flex ratio value:
 275          * CPU ratio value controls the maximum processor non-turbo ratio.
 276          * Valid Range 0 to 63.
 277          * In general descriptor provides option to set default cpu flex ratio.
 278          * Default cpu flex ratio 0 ensures booting with non-turbo max frequency.
 279          * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
 280          * Only override CPU flex ratio to not boot with non-turbo max.
 281          */
 282         uint8_t cpu_ratio_override;
 283
 284         /* Skip CPU replacement check
 285          * 0: disable
 286          * 1: enable
 287          * Setting this option to skip CPU replacement check to avoid the forced MRC training
 288          * for the platforms with soldered down SOC.
 289          */
 290         uint8_t SkipCpuReplacementCheck;
 291
 292         /*
 293          * SLP_S3 Minimum Assertion Width Policy
 294          *  1 = 60us
 295          *  2 = 1ms
 296          *  3 = 50ms (default)
 297          *  4 = 2s
 298          */
 299         uint8_t PchPmSlpS3MinAssert;
 300
 301         /*
 302          * SLP_S4 Minimum Assertion Width Policy
 303          *  1 = 1s (default)
 304          *  2 = 2s
 305          *  3 = 3s
 306          *  4 = 4s
 307          */
 308         uint8_t PchPmSlpS4MinAssert;
 309
 310         /*
 311          * SLP_SUS Minimum Assertion Width Policy
 312          *  1 = 0ms
 313          *  2 = 500ms
 314          *  3 = 1s
 315          *  4 = 4s (default)
 316          */
 317         uint8_t PchPmSlpSusMinAssert;
 318
 319         /*
 320          * SLP_A Minimum Assertion Width Policy
 321          *  1 = 0ms
 322          *  2 = 4s
 323          *  3 = 98ms
 324          *  4 = 2s (default)
 325          */
 326         uint8_t PchPmSlpAMinAssert;
 327
 328         /*
 329          * PCH PM Reset Power Cycle Duration
 330          *  0 = 4s (default)
 331          *  1 = 1s
 332          *  2 = 2s
 333          *  3 = 3s
 334          *  4 = 4s
 335          *
 336          * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
 337          * stretch duration programmed in the following registers:
 338          *  - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
 339          *  - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
 340          *  - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
 341          *  - PM_CFG.SLP_LAN_MIN_ASST_WDTH
 342          */
 343         uint8_t PchPmPwrCycDur;
 344
 345         /*
 346          * FIVR RFI Frequency
 347          * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
 348          * 0: Auto.
 349          * Range varies based on XTAL clock:
 350          *    0-1918 (Up to 191.8HMz) for 24MHz clock;
 351          *    0-1535 (Up to 153.5MHz) for 19MHz clock.
 352          */
 353         uint16_t FivrRfiFrequency;
 354
 355         /*
 356          * FIVR RFI Spread Spectrum
 357          * Set the Spread Spectrum Range. <b>0: 0%</b>;
 358          * FIVR RFI Spread Spectrum, in 0.1% increments.
 359          * Range: 0.0% to 10.0% (0-100)
 360          */
 361         uint8_t FivrSpreadSpectrum;
 362 };
 363
 364 typedef struct soc_intel_jasperlake_config config_t;
 365
 366 #endif