2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
21 # stage selectors for x86
23 config ARCH_BOOTBLOCK_X86_32
27 select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK
29 config ARCH_VERSTAGE_X86_32
33 config ARCH_ROMSTAGE_X86_32
37 config ARCH_RAMSTAGE_X86_32
41 # stage selectors for x64
43 config ARCH_BOOTBLOCK_X86_64
47 select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK
49 config ARCH_VERSTAGE_X86_64
53 config ARCH_ROMSTAGE_X86_64
57 config ARCH_RAMSTAGE_X86_64
64 Allow a platform or processor to select to be compiled using
65 the '-march=i586' option instead of the typical '-march=i686'
67 # This is an SMP option. It relates to starting up APs.
68 # It is usually set in mainboard/*/Kconfig.
69 # TODO: Improve description.
70 config AP_IN_SIPI_WAIT
73 depends on ARCH_X86 && SMP
75 # Aligns 16bit entry code in bootblock so that hyper-threading CPUs
76 # can boot AP CPUs to enable their shared caches.
77 config SIPI_VECTOR_IN_ROM
91 # Traditionally BIOS region on SPI flash boot media was memory mapped right below
92 # 4G and it was the last region in the IFD. This way translation between CPU
93 # address space to flash address was trivial. However some IFDs on newer SoCs
94 # have BIOS region sandwiched between descriptor and other regions. Turning off
95 # this option enables soc code to provide custom mmap_boot.c which can be used to
96 # implement complex translation.
97 config X86_TOP4G_BOOTMEDIA_MAP
101 # This is something you almost certainly don't want to mess with.
102 # How many SIPIs do we send when starting up APs and cores?
103 # The answer in 2000 or so was '2'. Nowadays, on many systems,
104 # it is 1. Set a safe default here, and you can override it
105 # on reasonable platforms.
106 config NUM_IPI_STARTS
114 config LATE_CBMEM_INIT
117 Enable this in chipset's Kconfig if northbridge does not implement
118 early get_top_of_ram() call for romstage. CBMEM tables will be
119 allocated late in ramstage, after PCI devices resources are known.
123 default y if ARCH_X86
125 config BOOTBLOCK_DEBUG_SPINLOOP
129 Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
130 for a JTAG debugger to break into the execution sequence.
132 config BOOTBLOCK_MAINBOARD_INIT
135 config BOOTBLOCK_NORTHBRIDGE_INIT
138 config BOOTBLOCK_RESETS
141 config BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP
145 Select this value to provide a routine to save the BIST and timestamp
146 values. The default code places the BIST value in MM0 and the
147 timestamp value in MM2:MM1. Another file is necessary when the CPU
148 does not support the MMx register set.
150 config HAVE_CMOS_DEFAULT
153 config CMOS_DEFAULT_FILE
155 default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
156 depends on HAVE_CMOS_DEFAULT
158 config BOOTBLOCK_SOUTHBRIDGE_INIT
161 config IOAPIC_INTERRUPTS_ON_FSB
163 default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
165 config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
171 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
173 config ID_SECTION_OFFSET
177 # 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK.
178 config C_ENV_BOOTBLOCK_SIZE
182 # Default address romstage is to be linked at
187 # Default address verstage is to be linked at
192 # Use the post CAR infrastructure for tearing down cache-as-ram
193 # from a program loaded in RAM and subsequently loading ramstage.
197 config VERSTAGE_DEBUG_SPINLOOP
201 Add a spin (JMP .) in assembly_entry.S during early verstage to wait
202 for a JTAG debugger to break into the execution sequence.
204 config ROMSTAGE_DEBUG_SPINLOOP
208 Add a spin (JMP .) in assembly_entry.S during early romstage to wait
209 for a JTAG debugger to break into the execution sequence.