src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
  17 #define _PLATFORM_GNB_PCIE_COMPLEX_H
  18
  19 //GNB GPP Port4
  20 #define GNB_GPP_PORT4_PORT_PRESENT              1       //0:Disable 1:Enable
  21 #define GNB_GPP_PORT4_SPEED_MODE                2       //0:Auto 1:GEN1 2:GEN2
  22 #define GNB_GPP_PORT4_LINK_ASPM                 3       //0:Disable 1:L0s 2:L1 3:L0s+L1
  23 #define GNB_GPP_PORT4_CHANNEL_TYPE              4       //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
  24                                                                                          //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
  25 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0       //0:Disable 1:Basic 3:Enhanced
  26
  27 //GNB GPP Port5
  28 #define GNB_GPP_PORT5_PORT_PRESENT              0       //0:Disable 1:Enable
  29 #define GNB_GPP_PORT5_SPEED_MODE                2       //0:Auto 1:GEN1 2:GEN2
  30 #define GNB_GPP_PORT5_LINK_ASPM                 3       //0:Disable 1:L0s 2:L1 3:L0s+L1
  31 #define GNB_GPP_PORT5_CHANNEL_TYPE              4       //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
  32                                                                                          //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
  33 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0       //0:Disable 1:Basic 3:Enhanced
  34
  35 //GNB GPP Port6
  36 #define GNB_GPP_PORT6_PORT_PRESENT              0       //0:Disable 1:Enable
  37 #define GNB_GPP_PORT6_SPEED_MODE                2       //0:Auto 1:GEN1 2:GEN2
  38 #define GNB_GPP_PORT6_LINK_ASPM                 3       //0:Disable 1:L0s 2:L1 3:L0s+L1
  39 #define GNB_GPP_PORT6_CHANNEL_TYPE              4       //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
  40                                                                                          //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
  41 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0       //0:Disable 1:Basic 3:Enhanced
  42
  43 //GNB GPP Port7
  44 #define GNB_GPP_PORT7_PORT_PRESENT              0       //0:Disable 1:Enable
  45 #define GNB_GPP_PORT7_SPEED_MODE                2       //0:Auto 1:GEN1 2:GEN2
  46 #define GNB_GPP_PORT7_LINK_ASPM                 3       //0:Disable 1:L0s 2:L1 3:L0s+L1
  47 #define GNB_GPP_PORT7_CHANNEL_TYPE              4       //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
  48                                                                                          //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
  49 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0       //0:Disable 1:Basic 3:Enhanced
  50
  51 //GNB GPP Port8
  52 #define GNB_GPP_PORT8_PORT_PRESENT              1       //0:Disable 1:Enable
  53 #define GNB_GPP_PORT8_SPEED_MODE                2       //0:Auto 1:GEN1 2:GEN2
  54 #define GNB_GPP_PORT8_LINK_ASPM                 3       //0:Disable 1:L0s 2:L1 3:L0s+L1
  55 #define GNB_GPP_PORT8_CHANNEL_TYPE              4       //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
  56                                                                                          //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
  57 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0       //0:Disable 1:Basic 3:Enhanced
  58
  59
  60 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H