mb/google/hatch: Configure reset config to PLTRST for IOAPIC pads
[coreboot.git] / src / mainboard / ocp / monolake / irqroute.h
blobc3911be75b91379a26c3a35dfed41ecd2aeed4b0
1 /*
2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Google Inc.
5 * Copyright (C) 2015-2016 Intel Corp.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #ifndef IRQROUTE_H
18 #define IRQROUTE_H
20 #include <soc/irq.h>
21 #include <soc/pci_devs.h>
23 #define PCI_DEV_PIRQ_ROUTES \
24 PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
25 PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \
26 PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \
27 PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \
28 PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
29 PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
30 PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \
31 PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D)
34 * Route each PIRQ[A-H] to a PIC IRQ[0-15]
35 * Reserved: 0, 1, 2, 8, 13
36 * ACPI/SCI: 9
38 #define PIRQ_PIC_ROUTES \
39 PIRQ_PIC(A, 5), \
40 PIRQ_PIC(B, 6), \
41 PIRQ_PIC(C, 7), \
42 PIRQ_PIC(D, 10), \
43 PIRQ_PIC(E, 11), \
44 PIRQ_PIC(F, 12), \
45 PIRQ_PIC(G, 14), \
46 PIRQ_PIC(H, 15)
48 #endif /* IRQROUTE_H */