src/mainboard/biostar/am1ml/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2013 Sage Electronic Engineering, LLC
   6  * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 /* DefinitionBlock Statement */
  19 DefinitionBlock (
  20         "DSDT.AML",     /* Output filename */
  21         "DSDT",         /* Signature */
  22         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  23         "AMD   ",       /* OEMID */
  24         "COREBOOT",     /* TABLE ID */
  25         0x00010001      /* OEM Revision */
  26         )
  27 {       /* Start of ASL file */
  28         /* #include <arch/x86/acpi/debug.asl> */        /* Include global debug methods if needed */
  29
  30         /* Globals for the platform */
  31         #include "acpi/mainboard.asl"
  32
  33         /* Describe the USB Overcurrent pins */
  34         #include "acpi/usb_oc.asl"
  35
  36         /* PCI IRQ mapping for the Southbridge */
  37         #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
  38
  39         /* Describe the processor tree (\_PR) */
  40         #include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
  41
  42         /* Contains the supported sleep states for this chipset */
  43         #include <southbridge/amd/common/acpi/sleepstates.asl>
  44
  45         /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
  46         #include "acpi/sleep.asl"
  47
  48         /* stuff for sio */
  49         #include "acpi/flag0.asl"
  50
  51         /* System Bus */
  52         Scope(\_SB) { /* Start \_SB scope */
  53                 /* global utility methods expected within the \_SB scope */
  54                 #include <arch/x86/acpi/globutil.asl>
  55
  56                 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
  57                 #include "acpi/routing.asl"
  58
  59                 Device(PWRB) {
  60                         Name(_HID, EISAID("PNP0C0C"))
  61                         Name(_UID, 0xAA)
  62                         Name(_PRW, Package () {3, 0x04})
  63                         Name(_STA, 0x0B)
  64                 }
  65
  66                 Device(PCI0) {
  67                         /* Describe the AMD Northbridge */
  68                         #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
  69
  70                         /* Describe the AMD Fusion Controller Hub Southbridge */
  71                         #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
  72
  73                         /* sio fixup */
  74                         #include "acpi/sio.asl"
  75                 }
  76
  77                 /* Describe PCI INT[A-H] for the Southbridge */
  78                 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
  79
  80         } /* End \_SB scope */
  81
  82         /* Describe SMBUS for the Southbridge */
  83         #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
  84
  85         /* Define the General Purpose Events for the platform */
  86         #include "acpi/gpe.asl"
  87
  88         /* Define the Thermal zones and methods for the platform */
  89         #include "acpi/thermal.asl"
  90
  91         /* Define the System Indicators for the platform */
  92         #include "acpi/si.asl"
  93
  94 }
  95 /* End of ASL file */