| blob | cbf7ac6ade8c67a4d552bdb18b71f53ec871e863 |
1 /* $NoKeywords:$ */
2 /**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
14 * @e \$Revision: 65065 $ @e \$Date: 2012-02-07 01:26:53 -0600 (Tue, 07 Feb 2012) $
15 */
16 /*****************************************************************************
17 *
18 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ***************************************************************************/
45 /*****************************************************************************
46 *
47 * Start processing the user options: First, set default settings
48 *
49 ****************************************************************************/
51 /* Available options for image builds.
52 *
53 * As part of the image build for each image, define the options below to select the
54 * AGESA entry points included in that image. Turn these on in your option c file, not
55 * here.
56 */
57 // #define AGESA_ENTRY_INIT_RESET TRUE
58 // #define AGESA_ENTRY_INIT_RECOVERY TRUE
59 // #define AGESA_ENTRY_INIT_EARLY TRUE
60 // #define AGESA_ENTRY_INIT_POST TRUE
61 // #define AGESA_ENTRY_INIT_ENV TRUE
62 // #define AGESA_ENTRY_INIT_MID TRUE
63 // #define AGESA_ENTRY_INIT_LATE TRUE
64 // #define AGESA_ENTRY_INIT_S3SAVE TRUE
65 // #define AGESA_ENTRY_INIT_RESUME TRUE
66 // #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
67 // #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
69 /* Defaults for private/internal build control settings */
70 /* Available options for image builds.
71 *
72 * As part of the image build for each image, define the options below to select the
73 * AGESA entry points included in that image.
74 */
76 VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
77 //ModuleHeaderSignature
78 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
80 //ModuleIdentifier[8]
81 AGESA_ID,
82 //ModuleVersion[12]
83 AGESA_VERSION_STRING,
84 //ModuleDispatcher
86 //NextBlock
87 NULL
88 };
90 /* Process user desired AGESA entry points */
91 #ifndef AGESA_ENTRY_INIT_RESET
92 #define AGESA_ENTRY_INIT_RESET FALSE
93 #endif
95 #ifndef AGESA_ENTRY_INIT_RECOVERY
96 #define AGESA_ENTRY_INIT_RECOVERY FALSE
97 #endif
99 #ifndef AGESA_ENTRY_INIT_EARLY
100 #define AGESA_ENTRY_INIT_EARLY FALSE
101 #endif
103 #ifndef AGESA_ENTRY_INIT_POST
104 #define AGESA_ENTRY_INIT_POST FALSE
105 #endif
107 #ifndef AGESA_ENTRY_INIT_ENV
108 #define AGESA_ENTRY_INIT_ENV FALSE
109 #endif
111 #ifndef AGESA_ENTRY_INIT_MID
112 #define AGESA_ENTRY_INIT_MID FALSE
113 #endif
115 #ifndef AGESA_ENTRY_INIT_LATE
116 #define AGESA_ENTRY_INIT_LATE FALSE
117 #endif
119 #ifndef AGESA_ENTRY_INIT_S3SAVE
120 #define AGESA_ENTRY_INIT_S3SAVE FALSE
121 #endif
123 #ifndef AGESA_ENTRY_INIT_RESUME
124 #define AGESA_ENTRY_INIT_RESUME FALSE
125 #endif
127 #ifndef AGESA_ENTRY_INIT_LATE_RESTORE
128 #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
129 #endif
131 #ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
132 #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
133 #endif
135 /* Default the late AP entry point to off. It can be enabled
136 by any family that may need the late AP functionality, or
137 by any feature code that may need it. The IBVs no longer
138 have control over this entry point. */
139 #ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
140 #undef AGESA_ENTRY_LATE_RUN_AP_TASK
141 #endif
142 #define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
146 /* Process solution defined socket / family installations
147 *
148 * As part of the release package for each image, define the options below to select the
149 * AGESA processor support included in that image.
150 */
152 /* Default sockets to off */
153 #define OPTION_G34_SOCKET_SUPPORT FALSE
154 #define OPTION_C32_SOCKET_SUPPORT FALSE
155 #define OPTION_S1G3_SOCKET_SUPPORT FALSE
156 #define OPTION_S1G4_SOCKET_SUPPORT FALSE
157 #define OPTION_ASB2_SOCKET_SUPPORT FALSE
158 #define OPTION_FS1_SOCKET_SUPPORT FALSE
159 #define OPTION_FM1_SOCKET_SUPPORT FALSE
160 #define OPTION_FM2_SOCKET_SUPPORT FALSE
161 #define OPTION_FP1_SOCKET_SUPPORT FALSE
162 #define OPTION_FP2_SOCKET_SUPPORT FALSE
163 #define OPTION_FT1_SOCKET_SUPPORT FALSE
164 #define OPTION_AM3_SOCKET_SUPPORT FALSE
166 /* Default families to off */
167 #define OPTION_FAMILY10H FALSE
168 #define OPTION_FAMILY12H FALSE
169 #define OPTION_FAMILY14H FALSE
170 #define OPTION_FAMILY15H FALSE
171 #define OPTION_FAMILY15H_MODEL_0x FALSE
172 #define OPTION_FAMILY15H_MODEL_1x FALSE
175 /* Enable the appropriate socket support */
176 #ifdef INSTALL_G34_SOCKET_SUPPORT
177 #if INSTALL_G34_SOCKET_SUPPORT == TRUE
178 #undef OPTION_G34_SOCKET_SUPPORT
179 #define OPTION_G34_SOCKET_SUPPORT TRUE
180 #endif
181 #endif
183 #ifdef INSTALL_C32_SOCKET_SUPPORT
184 #if INSTALL_C32_SOCKET_SUPPORT == TRUE
185 #undef OPTION_C32_SOCKET_SUPPORT
186 #define OPTION_C32_SOCKET_SUPPORT TRUE
187 #endif
188 #endif
190 #ifdef INSTALL_S1G3_SOCKET_SUPPORT
191 #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE
192 #undef OPTION_S1G3_SOCKET_SUPPORT
193 #define OPTION_S1G3_SOCKET_SUPPORT TRUE
194 #endif
195 #endif
197 #ifdef INSTALL_S1G4_SOCKET_SUPPORT
198 #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE
199 #undef OPTION_S1G4_SOCKET_SUPPORT
200 #define OPTION_S1G4_SOCKET_SUPPORT TRUE
201 #endif
202 #endif
204 #ifdef INSTALL_ASB2_SOCKET_SUPPORT
205 #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE
206 #undef OPTION_ASB2_SOCKET_SUPPORT
207 #define OPTION_ASB2_SOCKET_SUPPORT TRUE
208 #endif
209 #endif
211 #ifdef INSTALL_FS1_SOCKET_SUPPORT
212 #if INSTALL_FS1_SOCKET_SUPPORT == TRUE
213 #undef OPTION_FS1_SOCKET_SUPPORT
214 #define OPTION_FS1_SOCKET_SUPPORT TRUE
215 #endif
216 #endif
219 #ifdef INSTALL_FM1_SOCKET_SUPPORT
220 #if INSTALL_FM1_SOCKET_SUPPORT == TRUE
221 #undef OPTION_FM1_SOCKET_SUPPORT
222 #define OPTION_FM1_SOCKET_SUPPORT TRUE
223 #endif
224 #endif
226 #ifdef INSTALL_FM2_SOCKET_SUPPORT
227 #if INSTALL_FM2_SOCKET_SUPPORT == TRUE
228 #undef OPTION_FM2_SOCKET_SUPPORT
229 #define OPTION_FM2_SOCKET_SUPPORT TRUE
230 #endif
231 #endif
234 #ifdef INSTALL_FP1_SOCKET_SUPPORT
235 #if INSTALL_FP1_SOCKET_SUPPORT == TRUE
236 #undef OPTION_FP1_SOCKET_SUPPORT
237 #define OPTION_FP1_SOCKET_SUPPORT TRUE
238 #endif
239 #endif
241 #ifdef INSTALL_FP2_SOCKET_SUPPORT
242 #if INSTALL_FP2_SOCKET_SUPPORT == TRUE
243 #undef OPTION_FP2_SOCKET_SUPPORT
244 #define OPTION_FP2_SOCKET_SUPPORT TRUE
245 #endif
246 #endif
248 #ifdef INSTALL_FT1_SOCKET_SUPPORT
249 #if INSTALL_FT1_SOCKET_SUPPORT == TRUE
250 #undef OPTION_FT1_SOCKET_SUPPORT
251 #define OPTION_FT1_SOCKET_SUPPORT TRUE
252 #endif
253 #endif
256 #ifdef INSTALL_AM3_SOCKET_SUPPORT
257 #if INSTALL_AM3_SOCKET_SUPPORT == TRUE
258 #undef OPTION_AM3_SOCKET_SUPPORT
259 #define OPTION_AM3_SOCKET_SUPPORT TRUE
260 #endif
261 #endif
264 /* Enable the appropriate family support */
265 // F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
266 #ifdef INSTALL_FAMILY_10_SUPPORT
267 #if INSTALL_FAMILY_10_SUPPORT == TRUE
268 #undef OPTION_FAMILY10H
269 #define OPTION_FAMILY10H TRUE
270 #endif
271 #endif
273 // F12 is supported in FP1, FS1, & FM1
274 #ifdef INSTALL_FAMILY_12_SUPPORT
275 #if INSTALL_FAMILY_12_SUPPORT == TRUE
276 #undef OPTION_FAMILY12H
277 #define OPTION_FAMILY12H TRUE
278 #endif
279 #endif
281 #ifdef INSTALL_FAMILY_14_SUPPORT
282 #if INSTALL_FAMILY_14_SUPPORT == TRUE
283 #undef OPTION_FAMILY14H
284 #define OPTION_FAMILY14H TRUE
285 #endif
286 #endif
288 // F15_0x is supported in G34, C32, & AM3
289 #ifdef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
290 #if INSTALL_FAMILY_15_MODEL_0x_SUPPORT == TRUE
291 #undef OPTION_FAMILY15H
292 #define OPTION_FAMILY15H TRUE
293 #undef OPTION_FAMILY15H_MODEL_0x
294 #define OPTION_FAMILY15H_MODEL_0x TRUE
295 #endif
296 #endif
298 // F15_1x is supported in FS1r2, FM2, & FP2
299 #ifdef INSTALL_FAMILY_15_MODEL_1x_SUPPORT
300 #if INSTALL_FAMILY_15_MODEL_1x_SUPPORT == TRUE
301 #undef OPTION_FAMILY15H
302 #define OPTION_FAMILY15H TRUE
303 #undef OPTION_FAMILY15H_MODEL_1x
304 #define OPTION_FAMILY15H_MODEL_1x TRUE
305 #endif
306 #endif
309 /* Turn off families not required by socket designations */
310 #if (OPTION_FAMILY10H == TRUE)
311 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
312 #undef OPTION_FAMILY10H
313 #define OPTION_FAMILY10H FALSE
314 #endif
315 #endif
317 #if (OPTION_FAMILY12H == TRUE)
318 #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
319 #undef OPTION_FAMILY12H
320 #define OPTION_FAMILY12H FALSE
321 #endif
322 #endif
324 #if (OPTION_FAMILY14H == TRUE)
325 #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
326 #undef OPTION_FAMILY14H
327 #define OPTION_FAMILY14H FALSE
328 #endif
329 #endif
331 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
332 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
333 #undef OPTION_FAMILY15H_MODEL_0x
334 #define OPTION_FAMILY15H_MODEL_0x FALSE
335 #endif
336 #endif
338 #if (OPTION_FAMILY15H_MODEL_1x == TRUE)
339 #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM2_SOCKET_SUPPORT == FALSE) && (OPTION_FP2_SOCKET_SUPPORT == FALSE)
340 #undef OPTION_FAMILY15H_MODEL_1x
341 #define OPTION_FAMILY15H_MODEL_1x FALSE
342 #endif
343 #endif
346 #if (OPTION_FAMILY15H_MODEL_0x == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE)
347 #undef OPTION_FAMILY15H
348 #define OPTION_FAMILY15H FALSE
349 #endif
352 /* Check for invalid combinations of socket/family */
353 #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
354 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
355 #error No G34 supported families included in the build
356 #endif
357 #endif
359 #if (OPTION_C32_SOCKET_SUPPORT == TRUE)
360 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
361 #error No C32 supported families included in the build
362 #endif
363 #endif
365 #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
366 #if (OPTION_FAMILY10H == FALSE)
367 #error No S1G3 supported families included in the build
368 #endif
369 #endif
371 #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
372 #if (OPTION_FAMILY10H == FALSE)
373 #error No S1G4 supported families included in the build
374 #endif
375 #endif
377 #if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
378 #if (OPTION_FAMILY10H == FALSE)
379 #error No ASB2 supported families included in the build
380 #endif
381 #endif
383 #if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
384 #if (OPTION_FAMILY12H == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE)
385 #error No FS1 supported families included in the build
386 #endif
387 #endif
390 #if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
391 #if (OPTION_FAMILY12H == FALSE)
392 #error No FM1 supported families included in the build
393 #endif
394 #endif
396 #if (OPTION_FM2_SOCKET_SUPPORT == TRUE)
397 #if (OPTION_FAMILY15H_MODEL_1x == FALSE)
398 #error No FM2 supported families included in the build
399 #endif
400 #endif
403 #if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
404 #if (OPTION_FAMILY12H == FALSE)
405 #error No FP1 supported families included in the build
406 #endif
407 #endif
409 #if (OPTION_FP2_SOCKET_SUPPORT == TRUE)
410 #if (OPTION_FAMILY15H_MODEL_1x == FALSE)
411 #error No FP2 supported families included in the build
412 #endif
413 #endif
415 #if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
416 #if (OPTION_FAMILY14H == FALSE)
417 #error No FT1 supported families included in the build
418 #endif
419 #endif
422 #if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
423 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
424 #error No AM3 supported families included in the build
425 #endif
426 #endif
429 /* Process AGESA private data
430 *
431 * Turn on appropriate CPU models and memory controllers,
432 * as well as some other memory controls.
433 */
435 /* Default all models to off */
436 #define OPTION_FAMILY10H_BL FALSE
437 #define OPTION_FAMILY10H_DA FALSE
438 #define OPTION_FAMILY10H_HY FALSE
439 #define OPTION_FAMILY10H_PH FALSE
440 #define OPTION_FAMILY10H_RB FALSE
441 #define OPTION_FAMILY12H_LN FALSE
442 #define OPTION_FAMILY14H_ON FALSE
443 #define OPTION_FAMILY15H_OR FALSE
444 #define OPTION_FAMILY15H_TN FALSE
445 #define OPTION_FAMILY15H_UNKNOWN FALSE
447 /* Default all memory controllers to off */
448 #define OPTION_MEMCTLR_DR FALSE
449 #define OPTION_MEMCTLR_HY FALSE
450 #define OPTION_MEMCTLR_OR FALSE
451 #define OPTION_MEMCTLR_C32 FALSE
452 #define OPTION_MEMCTLR_DA FALSE
453 #define OPTION_MEMCTLR_LN FALSE
454 #define OPTION_MEMCTLR_ON FALSE
455 #define OPTION_MEMCTLR_Ni FALSE
456 #define OPTION_MEMCTLR_PH FALSE
457 #define OPTION_MEMCTLR_RB FALSE
458 #define OPTION_MEMCTLR_TN FALSE
460 /* Default all memory controls to off */
461 #define OPTION_HW_WRITE_LEV_TRAINING FALSE
462 #define OPTION_SW_WRITE_LEV_TRAINING FALSE
463 #define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
464 #define OPTION_HW_DQS_REC_EN_TRAINING FALSE
465 #define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
466 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
467 #define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
468 #define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
469 #define OPTION_MAX_RD_LAT_TRAINING FALSE
470 #define OPTION_HW_DRAM_INIT FALSE
471 #define OPTION_SW_DRAM_INIT FALSE
472 #define OPTION_S3_MEM_SUPPORT FALSE
473 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
474 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
475 #define OPTION_PRE_MEM_INIT FALSE
476 #define OPTION_POST_MEM_INIT FALSE
478 /* Defaults for public user options */
479 #define OPTION_UDIMMS FALSE
480 #define OPTION_RDIMMS FALSE
481 #define OPTION_SODIMMS FALSE
482 #define OPTION_LRDIMMS FALSE
483 #define OPTION_DDR2 FALSE
484 #define OPTION_DDR3 FALSE
485 #define OPTION_ECC FALSE
486 #define OPTION_BANK_INTERLEAVE FALSE
487 #define OPTION_DCT_INTERLEAVE FALSE
488 #define OPTION_NODE_INTERLEAVE FALSE
489 #define OPTION_PARALLEL_TRAINING FALSE
490 #define OPTION_ONLINE_SPARE FALSE
491 #define OPTION_MEM_RESTORE FALSE
492 #define OPTION_DIMM_EXCLUDE FALSE
494 /* Default all CPU controls to off */
495 #define OPTION_MULTISOCKET FALSE
496 #define OPTION_SRAT FALSE
497 #define OPTION_SLIT FALSE
498 #define OPTION_HT_ASSIST FALSE
499 #define OPTION_ATM_MODE FALSE
500 #define OPTION_CPU_CORELEVLING FALSE
501 #define OPTION_MSG_BASED_C1E FALSE
502 #define OPTION_CPU_CFOH FALSE
503 #define OPTION_C6_STATE FALSE
504 #define OPTION_IO_CSTATE FALSE
505 #define OPTION_CPB FALSE
506 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
507 #define OPTION_CPU_PSTATE_HPC_MODE FALSE
508 #define OPTION_CPU_APM FALSE
509 #define OPTION_CPU_PSI FALSE
510 #define OPTION_CPU_HTC FALSE
511 #define OPTION_S3SCRIPT FALSE
512 #define OPTION_GFX_RECOVERY FALSE
514 /* Default FCH controls to off */
515 #define FCH_SUPPORT FALSE
517 /* Enable all private controls based on socket/family enables */
518 #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
519 #if (OPTION_FAMILY10H == TRUE)
520 #undef OPTION_FAMILY10H_HY
521 #define OPTION_FAMILY10H_HY TRUE
522 #undef OPTION_MEMCTLR_HY
523 #define OPTION_MEMCTLR_HY TRUE
524 #undef OPTION_HW_WRITE_LEV_TRAINING
525 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
526 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
527 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
528 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
529 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
530 #undef OPTION_MAX_RD_LAT_TRAINING
531 #define OPTION_MAX_RD_LAT_TRAINING TRUE
532 #undef OPTION_SW_DRAM_INIT
533 #define OPTION_SW_DRAM_INIT TRUE
534 #undef OPTION_S3_MEM_SUPPORT
535 #define OPTION_S3_MEM_SUPPORT TRUE
536 #undef OPTION_MULTISOCKET
537 #define OPTION_MULTISOCKET TRUE
538 #undef OPTION_SRAT
539 #define OPTION_SRAT TRUE
540 #undef OPTION_SLIT
541 #define OPTION_SLIT TRUE
542 #undef OPTION_HT_ASSIST
543 #define OPTION_HT_ASSIST TRUE
544 #undef OPTION_CPU_CORELEVLING
545 #define OPTION_CPU_CORELEVLING TRUE
546 #undef OPTION_MSG_BASED_C1E
547 #define OPTION_MSG_BASED_C1E TRUE
548 #undef OPTION_CPU_CFOH
549 #define OPTION_CPU_CFOH TRUE
550 #undef OPTION_UDIMMS
551 #define OPTION_UDIMMS TRUE
552 #undef OPTION_RDIMMS
553 #define OPTION_RDIMMS TRUE
554 #undef OPTION_SODIMMS
555 #define OPTION_SODIMMS TRUE
556 #undef OPTION_DDR3
557 #define OPTION_DDR3 TRUE
558 #undef OPTION_ECC
559 #define OPTION_ECC TRUE
560 #undef OPTION_BANK_INTERLEAVE
561 #define OPTION_BANK_INTERLEAVE TRUE
562 #undef OPTION_DCT_INTERLEAVE
563 #define OPTION_DCT_INTERLEAVE TRUE
564 #undef OPTION_NODE_INTERLEAVE
565 #define OPTION_NODE_INTERLEAVE TRUE
566 #undef OPTION_PARALLEL_TRAINING
567 #define OPTION_PARALLEL_TRAINING TRUE
568 #undef OPTION_MEM_RESTORE
569 #define OPTION_MEM_RESTORE TRUE
570 #undef OPTION_ONLINE_SPARE
571 #define OPTION_ONLINE_SPARE TRUE
572 #undef OPTION_DIMM_EXCLUDE
573 #define OPTION_DIMM_EXCLUDE TRUE
574 #endif
575 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
576 #undef OPTION_FAMILY15H_OR
577 #define OPTION_FAMILY15H_OR TRUE
578 #undef OPTION_FAMILY15H_UNKNOWN
579 #define OPTION_FAMILY15H_UNKNOWN TRUE
580 #undef OPTION_MEMCTLR_OR
581 #define OPTION_MEMCTLR_OR TRUE
582 #undef OPTION_HW_WRITE_LEV_TRAINING
583 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
584 #undef OPTION_CONTINOUS_PATTERN_GENERATION
585 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
586 #undef OPTION_HW_DQS_REC_EN_TRAINING
587 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
588 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
589 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
590 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
591 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
592 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
593 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
594 #undef OPTION_MAX_RD_LAT_TRAINING
595 #define OPTION_MAX_RD_LAT_TRAINING TRUE
596 #undef OPTION_SW_DRAM_INIT
597 #define OPTION_SW_DRAM_INIT TRUE
598 #undef OPTION_S3_MEM_SUPPORT
599 #define OPTION_S3_MEM_SUPPORT TRUE
600 #undef OPTION_MULTISOCKET
601 #define OPTION_MULTISOCKET TRUE
602 #undef OPTION_C6_STATE
603 #define OPTION_C6_STATE TRUE
604 #undef OPTION_IO_CSTATE
605 #define OPTION_IO_CSTATE TRUE
606 #undef OPTION_CPB
607 #define OPTION_CPB TRUE
608 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
609 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
610 #undef OPTION_CPU_APM
611 #define OPTION_CPU_APM TRUE
612 #undef OPTION_SRAT
613 #define OPTION_SRAT TRUE
614 #undef OPTION_SLIT
615 #define OPTION_SLIT TRUE
616 #undef OPTION_HT_ASSIST
617 #define OPTION_HT_ASSIST TRUE
618 #undef OPTION_ATM_MODE
619 #define OPTION_ATM_MODE TRUE
620 #undef OPTION_CPU_CORELEVLING
621 #define OPTION_CPU_CORELEVLING TRUE
622 #undef OPTION_MSG_BASED_C1E
623 #define OPTION_MSG_BASED_C1E TRUE
624 #undef OPTION_CPU_CFOH
625 #define OPTION_CPU_CFOH TRUE
626 #undef OPTION_UDIMMS
627 #define OPTION_UDIMMS TRUE
628 #undef OPTION_RDIMMS
629 #define OPTION_RDIMMS TRUE
630 #undef OPTION_SODIMMS
631 #define OPTION_SODIMMS TRUE
632 #undef OPTION_LRDIMMS
633 #define OPTION_LRDIMMS TRUE
634 #undef OPTION_DDR3
635 #define OPTION_DDR3 TRUE
636 #undef OPTION_ECC
637 #define OPTION_ECC TRUE
638 #undef OPTION_BANK_INTERLEAVE
639 #define OPTION_BANK_INTERLEAVE TRUE
640 #undef OPTION_DCT_INTERLEAVE
641 #define OPTION_DCT_INTERLEAVE TRUE
642 #undef OPTION_NODE_INTERLEAVE
643 #define OPTION_NODE_INTERLEAVE TRUE
644 #undef OPTION_MEM_RESTORE
645 #define OPTION_MEM_RESTORE TRUE
646 #undef OPTION_ONLINE_SPARE
647 #define OPTION_ONLINE_SPARE TRUE
648 #undef OPTION_DIMM_EXCLUDE
649 #define OPTION_DIMM_EXCLUDE TRUE
650 #endif
651 #endif
653 #if (OPTION_C32_SOCKET_SUPPORT == TRUE)
654 #if (OPTION_FAMILY10H == TRUE)
655 #undef OPTION_FAMILY10H_HY
656 #define OPTION_FAMILY10H_HY TRUE
657 #undef OPTION_MEMCTLR_C32
658 #define OPTION_MEMCTLR_C32 TRUE
659 #undef OPTION_HW_WRITE_LEV_TRAINING
660 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
661 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
662 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
663 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
664 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
665 #undef OPTION_MAX_RD_LAT_TRAINING
666 #define OPTION_MAX_RD_LAT_TRAINING TRUE
667 #undef OPTION_SW_DRAM_INIT
668 #define OPTION_SW_DRAM_INIT TRUE
669 #undef OPTION_S3_MEM_SUPPORT
670 #define OPTION_S3_MEM_SUPPORT TRUE
671 #undef OPTION_ADDR_TO_CS_TRANSLATOR
672 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
673 #undef OPTION_MULTISOCKET
674 #define OPTION_MULTISOCKET TRUE
675 #undef OPTION_SRAT
676 #define OPTION_SRAT TRUE
677 #undef OPTION_SLIT
678 #define OPTION_SLIT TRUE
679 #undef OPTION_HT_ASSIST
680 #define OPTION_HT_ASSIST TRUE
681 #undef OPTION_CPU_CORELEVLING
682 #define OPTION_CPU_CORELEVLING TRUE
683 #undef OPTION_MSG_BASED_C1E
684 #define OPTION_MSG_BASED_C1E TRUE
685 #undef OPTION_CPU_CFOH
686 #define OPTION_CPU_CFOH TRUE
687 #undef OPTION_UDIMMS
688 #define OPTION_UDIMMS TRUE
689 #undef OPTION_RDIMMS
690 #define OPTION_RDIMMS TRUE
691 #undef OPTION_SODIMMS
692 #define OPTION_SODIMMS TRUE
693 #undef OPTION_DDR3
694 #define OPTION_DDR3 TRUE
695 #undef OPTION_ECC
696 #define OPTION_ECC TRUE
697 #undef OPTION_BANK_INTERLEAVE
698 #define OPTION_BANK_INTERLEAVE TRUE
699 #undef OPTION_DCT_INTERLEAVE
700 #define OPTION_DCT_INTERLEAVE TRUE
701 #undef OPTION_NODE_INTERLEAVE
702 #define OPTION_NODE_INTERLEAVE TRUE
703 #undef OPTION_PARALLEL_TRAINING
704 #define OPTION_PARALLEL_TRAINING TRUE
705 #undef OPTION_MEM_RESTORE
706 #define OPTION_MEM_RESTORE TRUE
707 #undef OPTION_ONLINE_SPARE
708 #define OPTION_ONLINE_SPARE TRUE
709 #undef OPTION_DIMM_EXCLUDE
710 #define OPTION_DIMM_EXCLUDE TRUE
711 #endif
712 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
713 #undef OPTION_FAMILY15H_OR
714 #define OPTION_FAMILY15H_OR TRUE
715 #undef OPTION_FAMILY15H_UNKNOWN
716 #define OPTION_FAMILY15H_UNKNOWN TRUE
717 #undef OPTION_MEMCTLR_OR
718 #define OPTION_MEMCTLR_OR TRUE
719 #undef OPTION_HW_WRITE_LEV_TRAINING
720 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
721 #undef OPTION_CONTINOUS_PATTERN_GENERATION
722 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
723 #undef OPTION_HW_DQS_REC_EN_TRAINING
724 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
725 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
726 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
727 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
728 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
729 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
730 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
731 #undef OPTION_MAX_RD_LAT_TRAINING
732 #define OPTION_MAX_RD_LAT_TRAINING TRUE
733 #undef OPTION_SW_DRAM_INIT
734 #define OPTION_SW_DRAM_INIT TRUE
735 #undef OPTION_S3_MEM_SUPPORT
736 #define OPTION_S3_MEM_SUPPORT TRUE
737 #undef OPTION_ADDR_TO_CS_TRANSLATOR
738 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
739 #undef OPTION_MULTISOCKET
740 #define OPTION_MULTISOCKET TRUE
741 #undef OPTION_C6_STATE
742 #define OPTION_C6_STATE TRUE
743 #undef OPTION_IO_CSTATE
744 #define OPTION_IO_CSTATE TRUE
745 #undef OPTION_CPB
746 #define OPTION_CPB TRUE
747 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
748 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
749 #undef OPTION_CPU_APM
750 #define OPTION_CPU_APM TRUE
751 #undef OPTION_SRAT
752 #define OPTION_SRAT TRUE
753 #undef OPTION_SLIT
754 #define OPTION_SLIT TRUE
755 #undef OPTION_HT_ASSIST
756 #define OPTION_HT_ASSIST TRUE
757 #undef OPTION_ATM_MODE
758 #define OPTION_ATM_MODE TRUE
759 #undef OPTION_CPU_CORELEVLING
760 #define OPTION_CPU_CORELEVLING TRUE
761 #undef OPTION_MSG_BASED_C1E
762 #define OPTION_MSG_BASED_C1E TRUE
763 #undef OPTION_CPU_CFOH
764 #define OPTION_CPU_CFOH TRUE
765 #undef OPTION_UDIMMS
766 #define OPTION_UDIMMS TRUE
767 #undef OPTION_RDIMMS
768 #define OPTION_RDIMMS TRUE
769 #undef OPTION_SODIMMS
770 #define OPTION_SODIMMS TRUE
771 #undef OPTION_LRDIMMS
772 #define OPTION_LRDIMMS TRUE
773 #undef OPTION_DDR3
774 #define OPTION_DDR3 TRUE
775 #undef OPTION_ECC
776 #define OPTION_ECC TRUE
777 #undef OPTION_BANK_INTERLEAVE
778 #define OPTION_BANK_INTERLEAVE TRUE
779 #undef OPTION_DCT_INTERLEAVE
780 #define OPTION_DCT_INTERLEAVE TRUE
781 #undef OPTION_NODE_INTERLEAVE
782 #define OPTION_NODE_INTERLEAVE TRUE
783 #undef OPTION_MEM_RESTORE
784 #define OPTION_MEM_RESTORE TRUE
785 #undef OPTION_ONLINE_SPARE
786 #define OPTION_ONLINE_SPARE TRUE
787 #undef OPTION_DIMM_EXCLUDE
788 #define OPTION_DIMM_EXCLUDE TRUE
789 #endif
790 #endif
792 #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
793 #if (OPTION_FAMILY10H == TRUE)
794 #undef OPTION_FAMILY10H_BL
795 #define OPTION_FAMILY10H_BL TRUE
796 #undef OPTION_FAMILY10H_DA
797 #define OPTION_FAMILY10H_DA TRUE
798 #undef OPTION_MEMCTLR_DA
799 #define OPTION_MEMCTLR_DA TRUE
800 #undef OPTION_HW_WRITE_LEV_TRAINING
801 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
802 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
803 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
804 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
805 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
806 #undef OPTION_MAX_RD_LAT_TRAINING
807 #define OPTION_MAX_RD_LAT_TRAINING TRUE
808 #undef OPTION_SW_DRAM_INIT
809 #define OPTION_SW_DRAM_INIT TRUE
810 #undef OPTION_S3_MEM_SUPPORT
811 #define OPTION_S3_MEM_SUPPORT TRUE
812 #undef OPTION_CPU_CORELEVLING
813 #define OPTION_CPU_CORELEVLING TRUE
814 #undef OPTION_CPU_CFOH
815 #define OPTION_CPU_CFOH TRUE
816 #undef OPTION_UDIMMS
817 #define OPTION_UDIMMS TRUE
818 #undef OPTION_SODIMMS
819 #define OPTION_SODIMMS TRUE
820 #undef OPTION_DDR3
821 #define OPTION_DDR3 TRUE
822 #undef OPTION_ECC
823 #define OPTION_ECC TRUE
824 #undef OPTION_BANK_INTERLEAVE
825 #define OPTION_BANK_INTERLEAVE TRUE
826 #undef OPTION_DCT_INTERLEAVE
827 #define OPTION_DCT_INTERLEAVE TRUE
828 #undef OPTION_NODE_INTERLEAVE
829 #define OPTION_NODE_INTERLEAVE TRUE
830 #undef OPTION_PARALLEL_TRAINING
831 #define OPTION_PARALLEL_TRAINING TRUE
832 #undef OPTION_MEM_RESTORE
833 #define OPTION_MEM_RESTORE TRUE
834 #undef OPTION_ONLINE_SPARE
835 #define OPTION_ONLINE_SPARE TRUE
836 #undef OPTION_DIMM_EXCLUDE
837 #define OPTION_DIMM_EXCLUDE TRUE
838 #endif
839 #endif
841 #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
842 #if (OPTION_FAMILY10H == TRUE)
843 #undef OPTION_FAMILY10H_BL
844 #define OPTION_FAMILY10H_BL TRUE
845 #undef OPTION_FAMILY10H_DA
846 #define OPTION_FAMILY10H_DA TRUE
847 #undef OPTION_MEMCTLR_DA
848 #define OPTION_MEMCTLR_DA TRUE
849 #undef OPTION_HW_WRITE_LEV_TRAINING
850 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
851 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
852 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
853 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
854 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
855 #undef OPTION_MAX_RD_LAT_TRAINING
856 #define OPTION_MAX_RD_LAT_TRAINING TRUE
857 #undef OPTION_SW_DRAM_INIT
858 #define OPTION_SW_DRAM_INIT TRUE
859 #undef OPTION_S3_MEM_SUPPORT
860 #define OPTION_S3_MEM_SUPPORT TRUE
861 #undef OPTION_CPU_CORELEVLING
862 #define OPTION_CPU_CORELEVLING TRUE
863 #undef OPTION_CPU_CFOH
864 #define OPTION_CPU_CFOH TRUE
865 #undef OPTION_UDIMMS
866 #define OPTION_UDIMMS TRUE
867 #undef OPTION_SODIMMS
868 #define OPTION_SODIMMS TRUE
869 #undef OPTION_DDR3
870 #define OPTION_DDR3 TRUE
871 #undef OPTION_ECC
872 #define OPTION_ECC TRUE
873 #undef OPTION_BANK_INTERLEAVE
874 #define OPTION_BANK_INTERLEAVE TRUE
875 #undef OPTION_DCT_INTERLEAVE
876 #define OPTION_DCT_INTERLEAVE TRUE
877 #undef OPTION_NODE_INTERLEAVE
878 #define OPTION_NODE_INTERLEAVE TRUE
879 #undef OPTION_MEM_RESTORE
880 #define OPTION_MEM_RESTORE TRUE
881 #undef OPTION_DIMM_EXCLUDE
882 #define OPTION_DIMM_EXCLUDE TRUE
883 #endif
884 #endif
886 #if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
887 #if (OPTION_FAMILY10H == TRUE)
888 #undef OPTION_FAMILY10H_BL
889 #define OPTION_FAMILY10H_BL TRUE
890 #undef OPTION_FAMILY10H_DA
891 #define OPTION_FAMILY10H_DA TRUE
892 #undef OPTION_MEMCTLR_Ni
893 #define OPTION_MEMCTLR_Ni TRUE
894 #undef OPTION_HW_WRITE_LEV_TRAINING
895 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
896 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
897 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
898 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
899 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
900 #undef OPTION_MAX_RD_LAT_TRAINING
901 #define OPTION_MAX_RD_LAT_TRAINING TRUE
902 #undef OPTION_SW_DRAM_INIT
903 #define OPTION_SW_DRAM_INIT TRUE
904 #undef OPTION_S3_MEM_SUPPORT
905 #define OPTION_S3_MEM_SUPPORT TRUE
906 #undef OPTION_CPU_CORELEVLING
907 #define OPTION_CPU_CORELEVLING TRUE
908 #undef OPTION_CPU_CFOH
909 #define OPTION_CPU_CFOH TRUE
910 #undef OPTION_UDIMMS
911 #define OPTION_UDIMMS TRUE
912 #undef OPTION_SODIMMS
913 #define OPTION_SODIMMS TRUE
914 #undef OPTION_DDR3
915 #define OPTION_DDR3 TRUE
916 #undef OPTION_ECC
917 #define OPTION_ECC TRUE
918 #undef OPTION_BANK_INTERLEAVE
919 #define OPTION_BANK_INTERLEAVE TRUE
920 #undef OPTION_DCT_INTERLEAVE
921 #define OPTION_DCT_INTERLEAVE TRUE
922 #undef OPTION_NODE_INTERLEAVE
923 #define OPTION_NODE_INTERLEAVE TRUE
924 #undef OPTION_MEM_RESTORE
925 #define OPTION_MEM_RESTORE TRUE
926 #undef OPTION_DIMM_EXCLUDE
927 #define OPTION_DIMM_EXCLUDE TRUE
928 #endif
929 #endif
931 #if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
932 #if (OPTION_FAMILY12H == TRUE)
933 #undef OPTION_FAMILY12H_LN
934 #define OPTION_FAMILY12H_LN TRUE
935 #undef OPTION_MEMCTLR_LN
936 #define OPTION_MEMCTLR_LN TRUE
937 #undef OPTION_HW_WRITE_LEV_TRAINING
938 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
939 #undef OPTION_CONTINOUS_PATTERN_GENERATION
940 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
941 #undef OPTION_HW_DQS_REC_EN_TRAINING
942 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
943 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
944 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
945 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
946 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
947 #undef OPTION_MAX_RD_LAT_TRAINING
948 #define OPTION_MAX_RD_LAT_TRAINING TRUE
949 #undef OPTION_SW_DRAM_INIT
950 #define OPTION_SW_DRAM_INIT TRUE
951 #undef OPTION_S3_MEM_SUPPORT
952 #define OPTION_S3_MEM_SUPPORT TRUE
953 #undef OPTION_GFX_RECOVERY
954 #define OPTION_GFX_RECOVERY TRUE
955 #undef OPTION_C6_STATE
956 #define OPTION_C6_STATE TRUE
957 #undef OPTION_IO_CSTATE
958 #define OPTION_IO_CSTATE TRUE
959 #undef OPTION_CPB
960 #define OPTION_CPB TRUE
961 #undef OPTION_S3SCRIPT
962 #define OPTION_S3SCRIPT TRUE
963 #undef OPTION_UDIMMS
964 #define OPTION_UDIMMS TRUE
965 #undef OPTION_SODIMMS
966 #define OPTION_SODIMMS TRUE
967 #undef OPTION_DDR3
968 #define OPTION_DDR3 TRUE
969 #undef OPTION_BANK_INTERLEAVE
970 #define OPTION_BANK_INTERLEAVE TRUE
971 #undef OPTION_DCT_INTERLEAVE
972 #define OPTION_DCT_INTERLEAVE TRUE
973 #undef OPTION_MEM_RESTORE
974 #define OPTION_MEM_RESTORE TRUE
975 #undef OPTION_DIMM_EXCLUDE
976 #define OPTION_DIMM_EXCLUDE TRUE
977 #endif
978 #if (OPTION_FAMILY15H_MODEL_1x == TRUE)
979 #undef FCH_SUPPORT
980 #define FCH_SUPPORT TRUE
981 #undef OPTION_FAMILY15H_TN
982 #define OPTION_FAMILY15H_TN TRUE
983 #undef OPTION_MEMCTLR_TN
984 #define OPTION_MEMCTLR_TN TRUE
985 #undef OPTION_HW_WRITE_LEV_TRAINING
986 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
987 #undef OPTION_CONTINOUS_PATTERN_GENERATION
988 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
989 #undef OPTION_HW_DQS_REC_EN_TRAINING
990 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
991 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
992 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
993 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
994 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
995 #undef OPTION_MAX_RD_LAT_TRAINING
996 #define OPTION_MAX_RD_LAT_TRAINING TRUE
997 #undef OPTION_SW_DRAM_INIT
998 #define OPTION_SW_DRAM_INIT TRUE
999 #undef OPTION_S3_MEM_SUPPORT
1000 #define OPTION_S3_MEM_SUPPORT TRUE
1001 #undef OPTION_GFX_RECOVERY
1002 #define OPTION_GFX_RECOVERY TRUE
1003 #undef OPTION_CPU_CORELEVLING
1004 #define OPTION_CPU_CORELEVLING TRUE
1005 #undef OPTION_C6_STATE
1006 #define OPTION_C6_STATE TRUE
1007 #undef OPTION_IO_CSTATE
1008 #define OPTION_IO_CSTATE TRUE
1009 #undef OPTION_CPB
1010 #define OPTION_CPB TRUE
1011 #undef OPTION_CPU_PSI
1012 #define OPTION_CPU_PSI TRUE
1013 #undef OPTION_CPU_HTC
1014 #define OPTION_CPU_HTC TRUE
1015 #undef OPTION_S3SCRIPT
1016 #define OPTION_S3SCRIPT TRUE
1017 #undef OPTION_CPU_CFOH
1018 #define OPTION_CPU_CFOH TRUE
1019 #undef OPTION_UDIMMS
1020 #define OPTION_UDIMMS TRUE
1021 #undef OPTION_SODIMMS
1022 #define OPTION_SODIMMS TRUE
1023 #undef OPTION_DDR3
1024 #define OPTION_DDR3 TRUE
1025 #undef OPTION_BANK_INTERLEAVE
1026 #define OPTION_BANK_INTERLEAVE TRUE
1027 #undef OPTION_DCT_INTERLEAVE
1028 #define OPTION_DCT_INTERLEAVE TRUE
1029 #undef OPTION_MEM_RESTORE
1030 #define OPTION_MEM_RESTORE TRUE
1031 #undef OPTION_DIMM_EXCLUDE
1032 #define OPTION_DIMM_EXCLUDE TRUE
1033 #endif
1034 #endif
1036 #if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
1037 #if (OPTION_FAMILY12H == TRUE)
1038 #undef OPTION_FAMILY12H_LN
1039 #define OPTION_FAMILY12H_LN TRUE
1040 #undef OPTION_MEMCTLR_LN
1041 #define OPTION_MEMCTLR_LN TRUE
1042 #undef OPTION_HW_WRITE_LEV_TRAINING
1043 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1044 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1045 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1046 #undef OPTION_HW_DQS_REC_EN_TRAINING
1047 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1048 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1049 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
1050 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1051 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1052 #undef OPTION_MAX_RD_LAT_TRAINING
1053 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1054 #undef OPTION_SW_DRAM_INIT
1055 #define OPTION_SW_DRAM_INIT TRUE
1056 #undef OPTION_S3_MEM_SUPPORT
1057 #define OPTION_S3_MEM_SUPPORT TRUE
1058 #undef OPTION_GFX_RECOVERY
1059 #define OPTION_GFX_RECOVERY TRUE
1060 #undef OPTION_C6_STATE
1061 #define OPTION_C6_STATE TRUE
1062 #undef OPTION_IO_CSTATE
1063 #define OPTION_IO_CSTATE TRUE
1064 #undef OPTION_CPB
1065 #define OPTION_CPB TRUE
1066 #undef OPTION_S3SCRIPT
1067 #define OPTION_S3SCRIPT TRUE
1068 #undef OPTION_UDIMMS
1069 #define OPTION_UDIMMS TRUE
1070 #undef OPTION_SODIMMS
1071 #define OPTION_SODIMMS TRUE
1072 #undef OPTION_DDR3
1073 #define OPTION_DDR3 TRUE
1074 #undef OPTION_BANK_INTERLEAVE
1075 #define OPTION_BANK_INTERLEAVE TRUE
1076 #undef OPTION_DCT_INTERLEAVE
1077 #define OPTION_DCT_INTERLEAVE TRUE
1078 #undef OPTION_MEM_RESTORE
1079 #define OPTION_MEM_RESTORE TRUE
1080 #undef OPTION_DIMM_EXCLUDE
1081 #define OPTION_DIMM_EXCLUDE TRUE
1082 #endif
1083 #endif
1085 #if (OPTION_FM2_SOCKET_SUPPORT == TRUE)
1086 #if (OPTION_FAMILY15H_MODEL_1x == TRUE)
1087 #undef FCH_SUPPORT
1088 #define FCH_SUPPORT TRUE
1089 #undef OPTION_FAMILY15H_TN
1090 #define OPTION_FAMILY15H_TN TRUE
1091 #undef OPTION_MEMCTLR_TN
1092 #define OPTION_MEMCTLR_TN TRUE
1093 #undef OPTION_HW_WRITE_LEV_TRAINING
1094 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1095 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1096 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1097 #undef OPTION_HW_DQS_REC_EN_TRAINING
1098 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1099 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1100 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
1101 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1102 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1103 #undef OPTION_MAX_RD_LAT_TRAINING
1104 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1105 #undef OPTION_SW_DRAM_INIT
1106 #define OPTION_SW_DRAM_INIT TRUE
1107 #undef OPTION_S3_MEM_SUPPORT
1108 #define OPTION_S3_MEM_SUPPORT TRUE
1109 #undef OPTION_GFX_RECOVERY
1110 #define OPTION_GFX_RECOVERY TRUE
1111 #undef OPTION_CPU_HTC
1112 #define OPTION_CPU_HTC TRUE
1113 #undef OPTION_CPU_CORELEVLING
1114 #define OPTION_CPU_CORELEVLING TRUE
1115 #undef OPTION_C6_STATE
1116 #define OPTION_C6_STATE TRUE
1117 #undef OPTION_IO_CSTATE
1118 #define OPTION_IO_CSTATE TRUE
1119 #undef OPTION_CPB
1120 #define OPTION_CPB TRUE
1121 #undef OPTION_CPU_PSI
1122 #define OPTION_CPU_PSI TRUE
1123 #undef OPTION_S3SCRIPT
1124 #define OPTION_S3SCRIPT TRUE
1125 #undef OPTION_CPU_CFOH
1126 #define OPTION_CPU_CFOH TRUE
1127 #undef OPTION_UDIMMS
1128 #define OPTION_UDIMMS TRUE
1129 #undef OPTION_SODIMMS
1130 #define OPTION_SODIMMS TRUE
1131 #undef OPTION_DDR3
1132 #define OPTION_DDR3 TRUE
1133 #undef OPTION_BANK_INTERLEAVE
1134 #define OPTION_BANK_INTERLEAVE TRUE
1135 #undef OPTION_DCT_INTERLEAVE
1136 #define OPTION_DCT_INTERLEAVE TRUE
1137 #undef OPTION_MEM_RESTORE
1138 #define OPTION_MEM_RESTORE TRUE
1139 #undef OPTION_DIMM_EXCLUDE
1140 #define OPTION_DIMM_EXCLUDE TRUE
1141 #endif
1142 #endif
1144 #if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
1145 #if (OPTION_FAMILY12H == TRUE)
1146 #undef OPTION_FAMILY12H_LN
1147 #define OPTION_FAMILY12H_LN TRUE
1148 #undef OPTION_MEMCTLR_LN
1149 #define OPTION_MEMCTLR_LN TRUE
1150 #undef OPTION_HW_WRITE_LEV_TRAINING
1151 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1152 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1153 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1154 #undef OPTION_HW_DQS_REC_EN_TRAINING
1155 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1156 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1157 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
1158 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1159 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1160 #undef OPTION_MAX_RD_LAT_TRAINING
1161 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1162 #undef OPTION_SW_DRAM_INIT
1163 #define OPTION_SW_DRAM_INIT TRUE
1164 #undef OPTION_S3_MEM_SUPPORT
1165 #define OPTION_S3_MEM_SUPPORT TRUE
1166 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1167 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
1168 #undef OPTION_GFX_RECOVERY
1169 #define OPTION_GFX_RECOVERY TRUE
1170 #undef OPTION_C6_STATE
1171 #define OPTION_C6_STATE TRUE
1172 #undef OPTION_IO_CSTATE
1173 #define OPTION_IO_CSTATE TRUE
1174 #undef OPTION_CPB
1175 #define OPTION_CPB TRUE
1176 #undef OPTION_S3SCRIPT
1177 #define OPTION_S3SCRIPT TRUE
1178 #undef OPTION_UDIMMS
1179 #define OPTION_UDIMMS TRUE
1180 #undef OPTION_SODIMMS
1181 #define OPTION_SODIMMS TRUE
1182 #undef OPTION_DDR3
1183 #define OPTION_DDR3 TRUE
1184 #undef OPTION_BANK_INTERLEAVE
1185 #define OPTION_BANK_INTERLEAVE TRUE
1186 #undef OPTION_DCT_INTERLEAVE
1187 #define OPTION_DCT_INTERLEAVE TRUE
1188 #undef OPTION_MEM_RESTORE
1189 #define OPTION_MEM_RESTORE TRUE
1190 #undef OPTION_ONLINE_SPARE
1191 #define OPTION_ONLINE_SPARE TRUE
1192 #undef OPTION_DIMM_EXCLUDE
1193 #define OPTION_DIMM_EXCLUDE TRUE
1194 #endif
1195 #endif
1197 #if (OPTION_FP2_SOCKET_SUPPORT == TRUE)
1198 #if (OPTION_FAMILY15H_MODEL_1x == TRUE)
1199 #undef FCH_SUPPORT
1200 #define FCH_SUPPORT TRUE
1201 #undef OPTION_FAMILY15H_TN
1202 #define OPTION_FAMILY15H_TN TRUE
1203 #undef OPTION_MEMCTLR_TN
1204 #define OPTION_MEMCTLR_TN TRUE
1205 #undef OPTION_HW_WRITE_LEV_TRAINING
1206 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1207 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1208 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1209 #undef OPTION_HW_DQS_REC_EN_TRAINING
1210 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1211 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1212 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
1213 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1214 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1215 #undef OPTION_MAX_RD_LAT_TRAINING
1216 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1217 #undef OPTION_SW_DRAM_INIT
1218 #define OPTION_SW_DRAM_INIT TRUE
1219 #undef OPTION_S3_MEM_SUPPORT
1220 #define OPTION_S3_MEM_SUPPORT TRUE
1221 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1222 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
1223 #undef OPTION_GFX_RECOVERY
1224 #define OPTION_GFX_RECOVERY TRUE
1225 #undef OPTION_CPU_HTC
1226 #define OPTION_CPU_HTC TRUE
1227 #undef OPTION_CPU_CORELEVLING
1228 #define OPTION_CPU_CORELEVLING TRUE
1229 #undef OPTION_C6_STATE
1230 #define OPTION_C6_STATE TRUE
1231 #undef OPTION_IO_CSTATE
1232 #define OPTION_IO_CSTATE TRUE
1233 #undef OPTION_CPB
1234 #define OPTION_CPB TRUE
1235 #undef OPTION_CPU_PSI
1236 #define OPTION_CPU_PSI TRUE
1237 #undef OPTION_S3SCRIPT
1238 #define OPTION_S3SCRIPT TRUE
1239 #undef OPTION_CPU_CFOH
1240 #define OPTION_CPU_CFOH TRUE
1241 #undef OPTION_UDIMMS
1242 #define OPTION_UDIMMS TRUE
1243 #undef OPTION_SODIMMS
1244 #define OPTION_SODIMMS TRUE
1245 #undef OPTION_DDR3
1246 #define OPTION_DDR3 TRUE
1247 #undef OPTION_BANK_INTERLEAVE
1248 #define OPTION_BANK_INTERLEAVE TRUE
1249 #undef OPTION_DCT_INTERLEAVE
1250 #define OPTION_DCT_INTERLEAVE TRUE
1251 #undef OPTION_MEM_RESTORE
1252 #define OPTION_MEM_RESTORE TRUE
1253 #undef OPTION_DIMM_EXCLUDE
1254 #define OPTION_DIMM_EXCLUDE TRUE
1255 #endif
1256 #endif
1258 #if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
1259 #if (OPTION_FT1_T_SOCKET_SUPPORT == TRUE)
1260 #undef FCH_SUPPORT
1261 #define FCH_SUPPORT TRUE
1262 #endif
1263 #if (OPTION_FAMILY14H == TRUE)
1264 #if (OPTION_FAMILY14H_FCH == TRUE)
1265 #undef FCH_SUPPORT
1266 #define FCH_SUPPORT TRUE
1267 #endif
1268 #undef OPTION_FAMILY14H_ON
1269 #define OPTION_FAMILY14H_ON TRUE
1270 #undef OPTION_MEMCTLR_ON
1271 #define OPTION_MEMCTLR_ON TRUE
1272 #undef OPTION_HW_WRITE_LEV_TRAINING
1273 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1274 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1275 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1276 #undef OPTION_MAX_RD_LAT_TRAINING
1277 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1278 #undef OPTION_HW_DQS_REC_EN_TRAINING
1279 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1280 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1281 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
1282 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1283 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1284 #undef OPTION_SW_DRAM_INIT
1285 #define OPTION_SW_DRAM_INIT TRUE
1286 #undef OPTION_S3_MEM_SUPPORT
1287 #define OPTION_S3_MEM_SUPPORT TRUE
1288 #undef OPTION_GFX_RECOVERY
1289 #define OPTION_GFX_RECOVERY TRUE
1290 #undef OPTION_C6_STATE
1291 #define OPTION_C6_STATE TRUE
1292 #undef OPTION_IO_CSTATE
1293 #define OPTION_IO_CSTATE TRUE
1294 #undef OPTION_CPB
1295 #define OPTION_CPB TRUE
1296 #undef OPTION_S3SCRIPT
1297 #define OPTION_S3SCRIPT TRUE
1298 #undef OPTION_UDIMMS
1299 #define OPTION_UDIMMS TRUE
1300 #undef OPTION_SODIMMS
1301 #define OPTION_SODIMMS TRUE
1302 #undef OPTION_DDR3
1303 #define OPTION_DDR3 TRUE
1304 #undef OPTION_BANK_INTERLEAVE
1305 #define OPTION_BANK_INTERLEAVE TRUE
1306 #undef OPTION_MEM_RESTORE
1307 #define OPTION_MEM_RESTORE TRUE
1308 #undef OPTION_DIMM_EXCLUDE
1309 #define OPTION_DIMM_EXCLUDE TRUE
1310 #endif
1311 #endif
1314 #if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
1315 #if (OPTION_FAMILY10H == TRUE)
1316 #undef OPTION_FAMILY10H_BL
1317 #define OPTION_FAMILY10H_BL TRUE
1318 #undef OPTION_FAMILY10H_DA
1319 #define OPTION_FAMILY10H_DA TRUE
1320 #undef OPTION_FAMILY10H_PH
1321 #define OPTION_FAMILY10H_PH TRUE
1322 #undef OPTION_FAMILY10H_RB
1323 #define OPTION_FAMILY10H_RB TRUE
1324 #undef OPTION_MEMCTLR_RB
1325 #define OPTION_MEMCTLR_RB TRUE
1326 #undef OPTION_MEMCTLR_DA
1327 #define OPTION_MEMCTLR_DA TRUE
1328 #undef OPTION_MEMCTLR_PH
1329 #define OPTION_MEMCTLR_PH TRUE
1330 #undef OPTION_HW_WRITE_LEV_TRAINING
1331 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1332 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
1333 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
1334 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1335 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1336 #undef OPTION_MAX_RD_LAT_TRAINING
1337 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1338 #undef OPTION_SW_DRAM_INIT
1339 #define OPTION_SW_DRAM_INIT TRUE
1340 #undef OPTION_S3_MEM_SUPPORT
1341 #define OPTION_S3_MEM_SUPPORT TRUE
1342 #undef OPTION_CPU_CORELEVLING
1343 #define OPTION_CPU_CORELEVLING TRUE
1344 #undef OPTION_CPU_CFOH
1345 #define OPTION_CPU_CFOH TRUE
1346 #undef OPTION_IO_CSTATE
1347 #define OPTION_IO_CSTATE TRUE
1348 #undef OPTION_CPB
1349 #define OPTION_CPB TRUE
1350 #undef OPTION_UDIMMS
1351 #define OPTION_UDIMMS TRUE
1352 #undef OPTION_SODIMMS
1353 #define OPTION_SODIMMS TRUE
1354 #undef OPTION_DDR3
1355 #define OPTION_DDR3 TRUE
1356 #undef OPTION_ECC
1357 #define OPTION_ECC TRUE
1358 #undef OPTION_BANK_INTERLEAVE
1359 #define OPTION_BANK_INTERLEAVE TRUE
1360 #undef OPTION_DCT_INTERLEAVE
1361 #define OPTION_DCT_INTERLEAVE TRUE
1362 #undef OPTION_NODE_INTERLEAVE
1363 #define OPTION_NODE_INTERLEAVE TRUE
1364 #undef OPTION_PARALLEL_TRAINING
1365 #define OPTION_PARALLEL_TRAINING TRUE
1366 #undef OPTION_MEM_RESTORE
1367 #define OPTION_MEM_RESTORE TRUE
1368 #undef OPTION_ONLINE_SPARE
1369 #define OPTION_ONLINE_SPARE TRUE
1370 #undef OPTION_DIMM_EXCLUDE
1371 #define OPTION_DIMM_EXCLUDE TRUE
1372 #endif
1373 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
1374 #undef OPTION_FAMILY15H_OR
1375 #define OPTION_FAMILY15H_OR TRUE
1376 #undef OPTION_FAMILY15H_UNKNOWN
1377 #define OPTION_FAMILY15H_UNKNOWN TRUE
1378 #undef OPTION_MEMCTLR_OR
1379 #define OPTION_MEMCTLR_OR TRUE
1380 #undef OPTION_HW_WRITE_LEV_TRAINING
1381 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1382 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1383 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1384 #undef OPTION_HW_DQS_REC_EN_TRAINING
1385 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1386 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1387 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
1388 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1389 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1390 #undef OPTION_MAX_RD_LAT_TRAINING
1391 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1392 #undef OPTION_SW_DRAM_INIT
1393 #define OPTION_SW_DRAM_INIT TRUE
1394 #undef OPTION_C6_STATE
1395 #define OPTION_C6_STATE TRUE
1396 #undef OPTION_IO_CSTATE
1397 #define OPTION_IO_CSTATE TRUE
1398 #undef OPTION_CPB
1399 #define OPTION_CPB TRUE
1400 #undef OPTION_CPU_APM
1401 #define OPTION_CPU_APM TRUE
1402 #undef OPTION_S3_MEM_SUPPORT
1403 #define OPTION_S3_MEM_SUPPORT TRUE
1404 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1405 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
1406 #undef OPTION_ATM_MODE
1407 #define OPTION_ATM_MODE TRUE
1408 #undef OPTION_CPU_CORELEVLING
1409 #define OPTION_CPU_CORELEVLING TRUE
1410 #undef OPTION_CPU_CFOH
1411 #define OPTION_CPU_CFOH TRUE
1412 #undef OPTION_MSG_BASED_C1E
1413 #define OPTION_MSG_BASED_C1E TRUE
1414 #undef OPTION_UDIMMS
1415 #define OPTION_UDIMMS TRUE
1416 #undef OPTION_RDIMMS
1417 #define OPTION_RDIMMS TRUE
1418 #undef OPTION_LRDIMMS
1419 #define OPTION_LRDIMMS TRUE
1420 #undef OPTION_SODIMMS
1421 #define OPTION_SODIMMS TRUE
1422 #undef OPTION_DDR3
1423 #define OPTION_DDR3 TRUE
1424 #undef OPTION_ECC
1425 #define OPTION_ECC TRUE
1426 #undef OPTION_BANK_INTERLEAVE
1427 #define OPTION_BANK_INTERLEAVE TRUE
1428 #undef OPTION_DCT_INTERLEAVE
1429 #define OPTION_DCT_INTERLEAVE TRUE
1430 #undef OPTION_NODE_INTERLEAVE
1431 #define OPTION_NODE_INTERLEAVE TRUE
1432 #undef OPTION_MEM_RESTORE
1433 #define OPTION_MEM_RESTORE TRUE
1434 #undef OPTION_ONLINE_SPARE
1435 #define OPTION_ONLINE_SPARE TRUE
1436 #undef OPTION_DIMM_EXCLUDE
1437 #define OPTION_DIMM_EXCLUDE TRUE
1438 #endif
1439 #endif
1444 #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY15H_TN == TRUE)
1445 #undef GNB_SUPPORT
1446 #define GNB_SUPPORT TRUE
1447 #endif
1449 #define OPTION_ACPI_PSTATES TRUE
1450 #define OPTION_WHEA TRUE
1451 #define OPTION_DMI TRUE
1452 #define OPTION_EARLY_SAMPLES FALSE
1453 #define CFG_ACPI_PSTATES_PPC TRUE
1454 #define CFG_ACPI_PSTATES_PCT TRUE
1455 #define CFG_ACPI_PSTATES_PSD TRUE
1456 #define CFG_ACPI_PSTATES_PSS TRUE
1457 #define CFG_ACPI_PSTATES_XPSS TRUE
1458 #define CFG_ACPI_PSTATE_PSD_INDPX FALSE
1459 #define CFG_VRM_HIGH_SPEED_ENABLE FALSE
1460 #define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
1461 #define OPTION_ALIB TRUE
1462 /*---------------------------------------------------------------------------
1463 * Processing the options: Second, process the user's selections
1464 *--------------------------------------------------------------------------*/
1465 #ifdef BLDOPT_REMOVE_DDR3_SUPPORT
1466 #if BLDOPT_REMOVE_DDR3_SUPPORT == TRUE
1467 #undef OPTION_DDR3
1468 #define OPTION_DDR3 FALSE
1469 #endif
1470 #endif
1471 #ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
1472 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
1473 #undef OPTION_MULTISOCKET
1474 #define OPTION_MULTISOCKET FALSE
1475 #endif
1476 #endif
1477 #ifdef BLDOPT_REMOVE_ECC_SUPPORT
1478 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
1479 #undef OPTION_ECC
1480 #define OPTION_ECC FALSE
1481 #endif
1482 #endif
1483 #ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
1484 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
1485 #undef OPTION_UDIMMS
1486 #define OPTION_UDIMMS FALSE
1487 #endif
1488 #endif
1489 #ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
1490 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
1491 #undef OPTION_RDIMMS
1492 #define OPTION_RDIMMS FALSE
1493 #endif
1494 #endif
1495 #ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
1496 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
1497 #undef OPTION_SODIMMS
1498 #define OPTION_SODIMMS FALSE
1499 #endif
1500 #endif
1501 #ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
1502 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
1503 #undef OPTION_LRDIMMS
1504 #define OPTION_LRDIMMS FALSE
1505 #endif
1506 #endif
1507 #ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
1508 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
1509 #undef OPTION_BANK_INTERLEAVE
1510 #define OPTION_BANK_INTERLEAVE FALSE
1511 #endif
1512 #endif
1513 #ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
1514 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
1515 #undef OPTION_DCT_INTERLEAVE
1516 #define OPTION_DCT_INTERLEAVE FALSE
1517 #endif
1518 #endif
1519 #ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
1520 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
1521 #undef OPTION_NODE_INTERLEAVE
1522 #define OPTION_NODE_INTERLEAVE FALSE
1523 #endif
1524 #endif
1525 #ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
1526 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
1527 #undef OPTION_PARALLEL_TRAINING
1528 #define OPTION_PARALLEL_TRAINING FALSE
1529 #endif
1530 #endif
1531 #ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
1532 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
1533 #undef OPTION_ONLINE_SPARE
1534 #define OPTION_ONLINE_SPARE FALSE
1535 #endif
1536 #endif
1537 #ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
1538 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
1539 #undef OPTION_MEM_RESTORE
1540 #define OPTION_MEM_RESTORE FALSE
1541 #endif
1542 #endif
1543 #ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
1544 #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
1545 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1546 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
1547 #endif
1548 #endif
1549 #ifdef BLDOPT_REMOVE_ACPI_PSTATES
1550 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
1551 #undef OPTION_ACPI_PSTATES
1552 #define OPTION_ACPI_PSTATES FALSE
1553 #endif
1554 #endif
1555 #ifdef BLDOPT_REMOVE_SRAT
1556 #if BLDOPT_REMOVE_SRAT == TRUE
1557 #undef OPTION_SRAT
1558 #define OPTION_SRAT FALSE
1559 #endif
1560 #endif
1561 #ifdef BLDOPT_REMOVE_SLIT
1562 #if BLDOPT_REMOVE_SLIT == TRUE
1563 #undef OPTION_SLIT
1564 #define OPTION_SLIT FALSE
1565 #endif
1566 #endif
1567 #ifdef BLDOPT_REMOVE_WHEA
1568 #if BLDOPT_REMOVE_WHEA == TRUE
1569 #undef OPTION_WHEA
1570 #define OPTION_WHEA FALSE
1571 #endif
1572 #endif
1573 #ifdef BLDOPT_REMOVE_DMI
1574 #if BLDOPT_REMOVE_DMI == TRUE
1575 #undef OPTION_DMI
1576 #define OPTION_DMI FALSE
1577 #endif
1578 #endif
1579 #ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
1580 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
1581 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1582 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
1583 #endif
1584 #endif
1586 #ifdef BLDOPT_REMOVE_HT_ASSIST
1587 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
1588 #undef OPTION_HT_ASSIST
1589 #define OPTION_HT_ASSIST FALSE
1590 #endif
1591 #endif
1593 #ifdef BLDOPT_REMOVE_ATM_MODE
1594 #if BLDOPT_REMOVE_ATM_MODE == TRUE
1595 #undef OPTION_ATM_MODE
1596 #define OPTION_ATM_MODE FALSE
1597 #endif
1598 #endif
1600 #ifdef BLDOPT_REMOVE_MSG_BASED_C1E
1601 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
1602 #undef OPTION_MSG_BASED_C1E
1603 #define OPTION_MSG_BASED_C1E FALSE
1604 #endif
1605 #endif
1607 #ifdef BLDOPT_REMOVE_C6_STATE
1608 #if BLDOPT_REMOVE_C6_STATE == TRUE
1609 #undef OPTION_C6_STATE
1610 #define OPTION_C6_STATE FALSE
1611 #endif
1612 #endif
1614 #ifdef BLDOPT_REMOVE_GFX_RECOVERY
1615 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
1616 #undef OPTION_GFX_RECOVERY
1617 #define OPTION_GFX_RECOVERY FALSE
1618 #endif
1619 #endif
1622 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
1623 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
1624 #undef CFG_ACPI_PSTATES_PPC
1625 #define CFG_ACPI_PSTATES_PPC FALSE
1626 #endif
1627 #endif
1629 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
1630 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
1631 #undef CFG_ACPI_PSTATES_PCT
1632 #define CFG_ACPI_PSTATES_PCT FALSE
1633 #endif
1634 #endif
1636 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
1637 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
1638 #undef CFG_ACPI_PSTATES_PSD
1639 #define CFG_ACPI_PSTATES_PSD FALSE
1640 #endif
1641 #endif
1643 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
1644 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
1645 #undef CFG_ACPI_PSTATES_PSS
1646 #define CFG_ACPI_PSTATES_PSS FALSE
1647 #endif
1648 #endif
1650 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
1651 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
1652 #undef CFG_ACPI_PSTATES_XPSS
1653 #define CFG_ACPI_PSTATES_XPSS FALSE
1654 #endif
1655 #endif
1657 #ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
1658 #if BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT == TRUE
1659 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
1660 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
1661 #endif
1662 #endif
1664 #ifdef BLDCFG_PSTATE_HPC_MODE
1665 #if BLDCFG_PSTATE_HPC_MODE == TRUE
1666 #undef OPTION_CPU_PSTATE_HPC_MODE
1667 #define OPTION_CPU_PSTATE_HPC_MODE TRUE
1668 #endif
1669 #endif
1671 #ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
1672 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
1673 #undef CFG_ACPI_PSTATE_PSD_INDPX
1674 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
1675 #endif
1676 #endif
1678 #ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
1679 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
1680 #undef CFG_VRM_HIGH_SPEED_ENABLE
1681 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
1682 #endif
1683 #endif
1685 #ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
1686 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
1687 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
1688 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
1689 #endif
1690 #endif
1692 #ifdef BLDCFG_STARTING_BUSNUM
1693 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
1694 #else
1695 #define CFG_STARTING_BUSNUM (0)
1696 #endif
1698 #ifdef BLDCFG_AMD_PLATFORM_TYPE
1699 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
1700 #else
1701 #define CFG_AMD_PLATFORM_TYPE 0
1702 #endif
1706 #ifdef BLDCFG_MAXIMUM_BUSNUM
1707 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
1708 #else
1709 #define CFG_MAXIMUM_BUSNUM (0xF8)
1710 #endif
1712 #ifdef BLDCFG_ALLOCATED_BUSNUM
1713 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
1714 #else
1715 #define CFG_ALLOCATED_BUSNUM (0x20)
1716 #endif
1718 #ifdef BLDCFG_BUID_SWAP_LIST
1719 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
1720 #else
1721 #define CFG_BUID_SWAP_LIST (NULL)
1722 #endif
1724 #ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
1725 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
1726 #else
1727 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
1728 #endif
1730 #ifdef BLDCFG_HTFABRIC_LIMITS_LIST
1731 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
1732 #else
1733 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
1734 #endif
1736 #ifdef BLDCFG_HTCHAIN_LIMITS_LIST
1737 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
1738 #else
1739 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
1740 #endif
1742 #ifdef BLDCFG_BUS_NUMBERS_LIST
1743 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
1744 #else
1745 #define CFG_BUS_NUMBERS_LIST (NULL)
1746 #endif
1748 #ifdef BLDCFG_IGNORE_LINK_LIST
1749 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
1750 #else
1751 #define CFG_IGNORE_LINK_LIST (NULL)
1752 #endif
1754 #ifdef BLDCFG_LINK_SKIP_REGANG_LIST
1755 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
1756 #else
1757 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
1758 #endif
1760 #ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
1761 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
1762 #else
1763 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
1764 #endif
1766 #ifdef BLDCFG_USE_UNIT_ID_CLUMPING
1767 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
1768 #else
1769 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
1770 #endif
1772 #ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
1773 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
1774 #else
1775 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
1776 #endif
1778 #ifdef BLDCFG_USE_HT_ASSIST
1779 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
1780 #else
1781 #define CFG_USE_HT_ASSIST (TRUE)
1782 #endif
1784 #ifdef BLDCFG_USE_ATM_MODE
1785 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
1786 #else
1787 #define CFG_USE_ATM_MODE (TRUE)
1788 #endif
1790 #ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
1791 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
1792 #else
1793 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
1794 #endif
1796 #ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
1797 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
1798 #else
1799 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (HARDWARE_PREFETCHER_AUTO)
1800 #endif
1802 #ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
1803 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
1804 #else
1805 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (SOFTWARE_PREFETCHES_AUTO)
1806 #endif
1808 #ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
1809 #define CFG_PERFORMANCE_DRAM_PREFETCHER (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
1810 #else
1811 #define CFG_PERFORMANCE_DRAM_PREFETCHER (DRAM_PREFETCHER_AUTO)
1812 #endif
1814 #ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
1815 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
1816 #else
1817 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
1818 #endif
1820 #ifdef BLDCFG_VRM_ADDITIONAL_DELAY
1821 #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY)
1822 #else
1823 #define CFG_VRM_ADDITIONAL_DELAY (0)
1824 #endif
1826 #ifdef BLDCFG_VRM_CURRENT_LIMIT
1827 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
1828 #else
1829 #define CFG_VRM_CURRENT_LIMIT 0
1830 #endif
1832 #ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
1833 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
1834 #else
1835 #define CFG_VRM_LOW_POWER_THRESHOLD 0
1836 #endif
1838 #ifdef BLDCFG_VRM_SLEW_RATE
1839 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
1840 #else
1841 #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
1842 #endif
1844 #ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
1845 #ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1846 #error BLDCFG: BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT is defined. Deprecated BLDCFG_VRM_INRUSH_CURRENT_LIMIT should not be defined.
1847 #endif
1848 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
1849 #else
1850 #ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1851 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1852 #else
1853 #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (0)
1854 #endif
1855 #endif
1857 #ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
1858 #ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1859 #error BLDCFG: BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT is defined. Deprecated BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT should not be defined.
1860 #endif
1861 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
1862 #else
1863 #ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1864 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1865 #else
1866 #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (0)
1867 #endif
1868 #endif
1870 #ifdef BLDCFG_VRM_SVI_OCP_LEVEL
1871 #define CFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_SVI_OCP_LEVEL
1872 #else
1873 #define CFG_VRM_SVI_OCP_LEVEL 0
1874 #endif
1876 #ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL
1877 #define CFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_SVI_OCP_LEVEL
1878 #else
1879 #define CFG_VRM_NB_SVI_OCP_LEVEL 0
1880 #endif
1882 #ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
1883 #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
1884 #else
1885 #define CFG_VRM_NB_ADDITIONAL_DELAY (0)
1886 #endif
1888 #ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
1889 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
1890 #else
1891 #define CFG_VRM_NB_CURRENT_LIMIT (0)
1892 #endif
1894 #ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1895 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1896 #else
1897 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
1898 #endif
1900 #ifdef BLDCFG_VRM_NB_SLEW_RATE
1901 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
1902 #else
1903 #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
1904 #endif
1906 #ifdef BLDCFG_PLAT_NUM_IO_APICS
1907 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
1908 #else
1909 #define CFG_PLAT_NUM_IO_APICS 0
1910 #endif
1912 #ifdef BLDCFG_MEM_INIT_PSTATE
1913 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
1914 #else
1915 #define CFG_MEM_INIT_PSTATE 0
1916 #endif
1918 #ifdef BLDCFG_PLATFORM_C1E_MODE
1919 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
1920 #else
1921 #define CFG_C1E_MODE C1eModeDisabled
1922 #endif
1924 #ifdef BLDCFG_PLATFORM_C1E_OPDATA
1925 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
1926 #else
1927 #define CFG_C1E_OPDATA 0
1928 #endif
1930 #ifdef BLDCFG_PLATFORM_C1E_OPDATA1
1931 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
1932 #else
1933 #define CFG_C1E_OPDATA1 0
1934 #endif
1936 #ifdef BLDCFG_PLATFORM_C1E_OPDATA2
1937 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
1938 #else
1939 #define CFG_C1E_OPDATA2 0
1940 #endif
1942 #ifdef BLDCFG_PLATFORM_C1E_OPDATA3
1943 #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3
1944 #else
1945 #define CFG_C1E_OPDATA3 0
1946 #endif
1948 #ifdef BLDCFG_PLATFORM_CSTATE_MODE
1949 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
1950 #else
1951 #define CFG_CSTATE_MODE CStateModeC6
1952 #endif
1954 #ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
1955 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
1956 #else
1957 #define CFG_CSTATE_OPDATA 0
1958 #endif
1960 #ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1961 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1962 #else
1963 #define CFG_CSTATE_IO_BASE_ADDRESS 0
1964 #endif
1966 #ifdef BLDCFG_PLATFORM_CPB_MODE
1967 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
1968 #else
1969 #define CFG_CPB_MODE CpbModeAuto
1970 #endif
1972 #ifdef BLDCFG_CORE_LEVELING_MODE
1973 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
1974 #else
1975 #define CFG_CORE_LEVELING_MODE 0
1976 #endif
1978 #ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
1979 #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE
1980 #else
1981 #define CFG_AMD_PSTATE_CAP_VALUE 0
1982 #endif
1984 #ifdef BLDCFG_HEAP_DRAM_ADDRESS
1985 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
1986 #else
1987 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
1988 #endif
1990 #ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1991 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1992 #else
1993 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
1994 #endif
1996 #ifdef BLDCFG_MEMORY_MODE_UNGANGED
1997 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
1998 #else
1999 #define CFG_MEMORY_MODE_UNGANGED TRUE
2000 #endif
2002 #ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
2003 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
2004 #else
2005 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
2006 #endif
2008 #ifdef BLDCFG_MEMORY_QUADRANK_TYPE
2009 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
2010 #else
2011 #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
2012 #endif
2014 #ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
2015 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
2016 #else
2017 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
2018 #endif
2020 #ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
2021 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
2022 #else
2023 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
2024 #endif
2026 #ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
2027 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
2028 #else
2029 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
2030 #endif
2032 #ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
2033 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
2034 #else
2035 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
2036 #endif
2038 #ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
2039 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
2040 #else
2041 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
2042 #endif
2044 #ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
2045 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
2046 #else
2047 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
2048 #endif
2050 #ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
2051 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
2052 #else
2053 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
2054 #endif
2056 #ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
2057 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
2058 #else
2059 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
2060 #endif
2062 #ifdef BLDCFG_MEMORY_POWER_DOWN
2063 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
2064 #else
2065 #define CFG_MEMORY_POWER_DOWN FALSE
2066 #endif
2068 #ifdef BLDCFG_POWER_DOWN_MODE
2069 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
2070 #else
2071 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
2072 #endif
2074 #ifdef BLDCFG_ONLINE_SPARE
2075 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
2076 #else
2077 #define CFG_ONLINE_SPARE FALSE
2078 #endif
2080 #ifdef BLDCFG_MEMORY_PARITY_ENABLE
2081 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
2082 #else
2083 #define CFG_MEMORY_PARITY_ENABLE FALSE
2084 #endif
2086 #ifdef BLDCFG_BANK_SWIZZLE
2087 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
2088 #else
2089 #define CFG_BANK_SWIZZLE TRUE
2090 #endif
2092 #ifdef BLDCFG_TIMING_MODE_SELECT
2093 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
2094 #else
2095 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
2096 #endif
2098 #ifdef BLDCFG_MEMORY_CLOCK_SELECT
2099 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
2100 #else
2101 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
2102 #endif
2104 #ifdef BLDCFG_DQS_TRAINING_CONTROL
2105 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
2106 #else
2107 #define CFG_DQS_TRAINING_CONTROL TRUE
2108 #endif
2110 #ifdef BLDCFG_IGNORE_SPD_CHECKSUM
2111 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
2112 #else
2113 #define CFG_IGNORE_SPD_CHECKSUM FALSE
2114 #endif
2116 #ifdef BLDCFG_USE_BURST_MODE
2117 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
2118 #else
2119 #define CFG_USE_BURST_MODE FALSE
2120 #endif
2122 #ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
2123 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
2124 #else
2125 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
2126 #endif
2128 #ifdef BLDCFG_ENABLE_ECC_FEATURE
2129 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
2130 #else
2131 #define CFG_ENABLE_ECC_FEATURE TRUE
2132 #endif
2134 #ifdef BLDCFG_ECC_REDIRECTION
2135 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
2136 #else
2137 #define CFG_ECC_REDIRECTION FALSE
2138 #endif
2140 #ifdef BLDCFG_SCRUB_DRAM_RATE
2141 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
2142 #else
2143 #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
2144 #endif
2146 #ifdef BLDCFG_SCRUB_L2_RATE
2147 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
2148 #else
2149 #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
2150 #endif
2152 #ifdef BLDCFG_SCRUB_L3_RATE
2153 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
2154 #else
2155 #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
2156 #endif
2158 #ifdef BLDCFG_SCRUB_IC_RATE
2159 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
2160 #else
2161 #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
2162 #endif
2164 #ifdef BLDCFG_SCRUB_DC_RATE
2165 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
2166 #else
2167 #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
2168 #endif
2170 #ifdef BLDCFG_ECC_SYNC_FLOOD
2171 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
2172 #else
2173 #define CFG_ECC_SYNC_FLOOD TRUE
2174 #endif
2176 #ifdef BLDCFG_ECC_SYMBOL_SIZE
2177 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
2178 #else
2179 #define CFG_ECC_SYMBOL_SIZE 0
2180 #endif
2182 #ifdef BLDCFG_1GB_ALIGN
2183 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
2184 #else
2185 #define CFG_1GB_ALIGN FALSE
2186 #endif
2188 #ifdef BLDCFG_UMA_ALLOCATION_MODE
2189 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
2190 #else
2191 #define CFG_UMA_MODE UMA_AUTO
2192 #endif
2194 #ifdef BLDCFG_FORCE_TRAINING_MODE
2195 #define CFG_FORCE_TRAIN_MODE BLDCFG_FORCE_TRAINING_MODE
2196 #else
2197 #define CFG_FORCE_TRAIN_MODE FORCE_TRAIN_AUTO
2198 #endif
2200 #ifdef BLDCFG_UMA_ALLOCATION_SIZE
2201 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
2202 #else
2203 #define CFG_UMA_SIZE 0
2204 #endif
2206 #ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
2207 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
2208 #else
2209 #define CFG_UMA_ABOVE4G FALSE
2210 #endif
2212 #ifdef BLDCFG_UMA_ALIGNMENT
2213 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
2214 #else
2215 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
2216 #endif
2218 #ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
2219 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
2220 #else
2221 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
2222 #endif
2224 #ifdef BLDCFG_S3_LATE_RESTORE
2225 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
2226 #else
2227 #define CFG_S3_LATE_RESTORE TRUE
2228 #endif
2230 #ifdef BLDCFG_USE_32_BYTE_REFRESH
2231 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
2232 #else
2233 #define CFG_USE_32_BYTE_REFRESH (FALSE)
2234 #endif
2236 #ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
2237 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
2238 #else
2239 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
2240 #endif
2242 #ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
2243 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
2244 #else
2245 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
2246 #endif
2248 #ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
2249 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
2250 #else
2251 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
2252 #endif
2254 #ifdef BLDCFG_CFG_GNB_HD_AUDIO
2255 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
2256 #else
2257 #define CFG_GNB_HD_AUDIO TRUE
2258 #endif
2260 #ifdef BLDCFG_CFG_ABM_SUPPORT
2261 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
2262 #else
2263 #define CFG_ABM_SUPPORT FALSE
2264 #endif
2266 #ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
2267 #define CFG_DYNAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
2268 #else
2269 #define CFG_DYNAMIC_REFRESH_RATE 0
2270 #endif
2272 #ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
2273 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
2274 #else
2275 #define CFG_LCD_BACK_LIGHT_CONTROL 0
2276 #endif
2278 #ifdef BLDCFG_STEREO_3D_PINOUT
2279 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
2280 #else
2281 #define CFG_GNB_STEREO_3D_PINOUT 0
2282 #endif
2284 #ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
2285 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT BLDCFG_REMOTE_DISPLAY_SUPPORT
2286 #else
2287 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT FALSE
2288 #endif
2290 // Define pin configuration for SYNCFLOOD
2291 // Default to FALSE (Use pin as SYNCFLOOD)
2292 #ifdef BLDCFG_USE_SYNCFLOOD_AS_NMI
2293 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI BLDCFG_USE_SYNCFLOOD_AS_NMI
2294 #else
2295 #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI FALSE
2296 #endif
2298 #ifdef BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
2299 #define CFG_GNB_THERMAL_SENSOR_CORRECTION BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
2300 #else
2301 #define CFG_GNB_THERMAL_SENSOR_CORRECTION 0
2302 #endif
2304 #ifdef BLDCFG_IGPU_SUBSYSTEM_ID
2305 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
2306 #else
2307 #define CFG_GNB_IGPU_SSID 0
2308 #endif
2310 #ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
2311 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
2312 #else
2313 #define CFG_GNB_HDAUDIO_SSID 0
2314 #endif
2316 #ifdef BLDCFG_IGPU_ENABLE_DISABLE_POLICY
2317 #define CFG_IGPU_ENABLE_DISABLE_POLICY BLDCFG_IGPU_ENABLE_DISABLE_POLICY
2318 #else
2319 #define CFG_IGPU_ENABLE_DISABLE_POLICY IGPU_DISABLE_AUTO
2320 #endif
2322 #ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
2323 #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
2324 #else
2325 #define CFG_GNB_PCIE_SSID 0x12341022ul
2326 #endif
2328 #ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
2329 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
2330 #else
2331 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
2332 #endif
2334 #ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
2335 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
2336 #else
2337 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
2338 #endif
2340 #ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
2341 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
2342 #else
2343 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
2344 #endif
2346 #ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
2347 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
2348 #else
2349 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000ul
2350 #endif
2352 #ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
2353 #define CFG_ENABLE_EXTERNAL_VREF BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
2354 #else
2355 #define CFG_ENABLE_EXTERNAL_VREF FALSE
2356 #endif
2359 #ifdef BLDOPT_REMOVE_ALIB
2360 #if BLDOPT_REMOVE_ALIB == TRUE
2361 #undef OPTION_ALIB
2362 #define OPTION_ALIB FALSE
2363 #else
2364 #undef OPTION_ALIB
2365 #define OPTION_ALIB TRUE
2366 #endif
2367 #endif
2369 #ifdef BLDOPT_REMOVE_FCH_COMPONENT
2370 #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
2371 #undef FCH_SUPPORT
2372 #define FCH_SUPPORT FALSE
2373 #endif
2374 #endif
2376 #ifdef BLDCFG_IOMMU_SUPPORT
2377 #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT
2378 #else
2379 #define CFG_IOMMU_SUPPORT TRUE
2380 #endif
2382 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
2383 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
2384 #else
2385 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0
2386 #endif
2388 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
2389 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
2390 #else
2391 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0
2392 #endif
2394 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
2395 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
2396 #else
2397 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0
2398 #endif
2400 #ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
2401 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
2402 #else
2403 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0
2404 #endif
2406 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
2407 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
2408 #else
2409 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0
2410 #endif
2412 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
2413 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
2414 #else
2415 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0
2416 #endif
2418 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
2419 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
2420 #else
2421 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0
2422 #endif
2424 #ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
2425 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
2426 #else
2427 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0
2428 #endif
2430 #ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
2431 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
2432 #else
2433 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0
2434 #endif
2437 // BLDCFG_LVDS_24BBP_PANEL_MODE
2438 // This specifies the LVDS 24 BBP mode.
2439 // 0 - Use LDI mode (default).
2440 // 1 - Use FPDI mode.
2441 #ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
2442 #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE
2443 #else
2444 #define CFG_LVDS_24BBP_PANEL_MODE 0
2445 #endif
2447 #ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
2448 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
2449 #else
2450 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
2451 #endif
2453 #ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
2454 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
2455 #else
2456 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
2457 #endif
2459 #ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
2460 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
2461 #else
2462 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
2463 #endif
2465 #ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
2466 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
2467 #else
2468 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
2469 #endif
2471 #ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
2472 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
2473 #else
2474 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
2475 #endif
2477 #ifdef BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
2478 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
2479 #else
2480 #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE FALSE
2481 #endif
2483 #ifdef BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
2484 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
2485 #else
2486 #define CFG_LVDS_MISC_VOLT_ADJUSTMENT 0
2487 #endif
2489 #ifdef BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
2490 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
2491 #else
2492 #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE FALSE
2493 #endif
2495 /*---------------------------------------------------------------------------
2496 * Processing the options: Third, perform the option cross checks
2497 *--------------------------------------------------------------------------*/
2498 // Assure that at least one type of memory support is included
2499 #if OPTION_UDIMMS == FALSE
2500 #if OPTION_RDIMMS == FALSE
2501 #if OPTION_SODIMMS == FALSE
2502 #if OPTION_LRDIMMS == FALSE
2503 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
2504 #endif
2505 #endif
2506 #endif
2507 #endif
2508 // Ensure at least one dimm type is capable
2509 #if CFG_MEMORY_RDIMM_CAPABLE == FALSE
2510 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
2511 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
2512 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
2513 #error BLDCFG: No dimm type is capable
2514 #endif
2515 #endif
2516 #endif
2517 #endif
2518 // Check LRDIMM CODE and LRDIMM CFG item
2519 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
2520 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
2521 #error Warning: LRDIMM capability is false, but LRIDMM support code included
2522 #endif
2523 #endif
2524 // Turn off multi-socket based features if only one node...
2525 #if OPTION_MULTISOCKET == FALSE
2526 #undef OPTION_PARALLEL_TRAINING
2527 #define OPTION_PARALLEL_TRAINING FALSE
2528 #undef OPTION_NODE_INTERLEAVE
2529 #define OPTION_NODE_INTERLEAVE FALSE
2530 #endif
2531 // Ensure the frequency limit is valid
2532 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR2133_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 1066)
2533 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
2534 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
2535 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
2536 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
2537 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
2538 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
2539 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
2540 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
2541 #error BLDCFG: Unsupported memory bus frequency
2542 #endif
2543 #endif
2544 #endif
2545 #endif
2546 #endif
2547 #endif
2548 #endif
2549 #endif
2550 #endif
2551 // Ensure timing mode is valid
2552 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
2553 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
2554 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
2555 #error BLDCFG: Invalid timing mode is set
2556 #endif
2557 #endif
2558 #endif
2559 // Ensure the scrub rate is valid
2560 #if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
2561 #error BLDCFG: Unsupported dram scrub rate set
2562 #endif
2563 #if CFG_SCRUB_L2_RATE > 0x16
2564 #error BLDCFG: Unsupported L2 scrubber rate set
2565 #endif
2566 #if CFG_SCRUB_L3_RATE > 0x16
2567 #error BLDCFG: unsupported L3 scrubber rate set
2568 #endif
2569 #if CFG_SCRUB_IC_RATE > 0x16
2570 #error BLDCFG: Unsupported Instruction cache scrub rate set
2571 #endif
2572 #if CFG_SCRUB_DC_RATE > 0x16
2573 #error BLDCFG: Unsupported Dcache scrub rate set
2574 #endif
2575 // Ensure Quad rank dimm type is valid
2576 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
2577 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
2578 #error BLDCFG: Invalid quad rank dimm type set
2579 #endif
2580 #endif
2581 // Ensure ECC symbol size is valid
2582 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
2583 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
2584 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
2585 #error BLDCFG: Invalid Ecc symbol size set
2586 #endif
2587 #endif
2588 #endif
2589 // Ensure power down mode is valid
2590 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
2591 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
2592 #error BLDCFG: Invalid power down mode set
2593 #endif
2594 #endif
2596 /*****************************************************************************
2597 *
2598 * Process the option logic, setting local control variables
2599 *
2600 ****************************************************************************/
2601 #if OPTION_ACPI_PSTATES == TRUE
2602 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
2603 #define OPTFCN_GATHER_DATA PStateGatherData
2604 #if OPTION_MULTISOCKET == TRUE
2605 #define OPTFCN_PSTATE_LEVELING PStateLeveling
2606 #else
2607 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2608 #endif
2609 #else
2610 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
2611 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
2612 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2613 #endif
2616 /*****************************************************************************
2617 *
2618 * Include the structure definitions for the defaults table structures
2619 *
2620 ****************************************************************************/
2652 /*****************************************************************************
2653 *
2654 * Generate the output structures (defaults tables)
2655 *
2656 ****************************************************************************/
2658 FCH_PLATFORM_POLICY FchUserOptions = {
2702 CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl
2703 };
2705 BUILD_OPT_CFG UserOptions = {
2711 },
2712 //Build Option Area
2726 FALSE,
2727 FALSE,
2735 //Build Configuration Area
2736 CFG_PCI_MMIO_BASE,
2737 CFG_PCI_MMIO_SIZE,
2738 {
2739 // CoreVrm
2740 {
2747 CFG_VRM_SVI_OCP_LEVEL // VrmSviOcpLevel
2748 },
2749 // NbVrm
2750 {
2757 CFG_VRM_NB_SVI_OCP_LEVEL // VrmNbSviOcpLevel
2758 }
2759 },
2773 {
2778 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
2779 // ADVANCED_PERFORMANCE_PROFILE
2780 {
2783 CFG_PERFORMANCE_DRAM_PREFETCHER // Dram prefetcher mode
2784 },
2785 CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode.
2786 },
2860 {{
2867 }},
2872 (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList
2877 {{
2881 }},
2883 };
2885 CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
2886 {
2887 #if AGESA_ENTRY_INIT_RESET == TRUE
2892 AMD_INIT_RESET_HANDLE
2893 },
2894 #endif
2896 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2901 AMD_INIT_POST_HANDLE
2902 },
2903 #endif
2905 #if AGESA_ENTRY_INIT_EARLY == TRUE
2910 AMD_INIT_EARLY_HANDLE
2911 },
2912 #endif
2914 #if AGESA_ENTRY_INIT_ENV == TRUE
2919 AMD_INIT_ENV_HANDLE
2920 },
2921 #endif
2923 #if AGESA_ENTRY_INIT_LATE == TRUE
2928 AMD_INIT_LATE_HANDLE
2929 },
2930 #endif
2932 #if AGESA_ENTRY_INIT_MID == TRUE
2937 AMD_INIT_MID_HANDLE
2938 },
2939 #endif
2941 #if AGESA_ENTRY_INIT_POST == TRUE
2946 AMD_INIT_POST_HANDLE
2947 },
2948 #endif
2950 #if AGESA_ENTRY_INIT_RESUME == TRUE
2955 AMD_INIT_RESUME_HANDLE
2956 },
2957 #endif
2959 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2964 AMD_S3_LATE_RESTORE_HANDLE
2965 },
2966 #endif
2968 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2973 AMD_S3_SAVE_HANDLE
2974 },
2975 #endif
2977 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2982 AMD_LATE_RUN_AP_TASK_HANDLE
2983 },
2984 #endif
2986 };
2990 CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
2991 {
2995 #if AGESA_ENTRY_INIT_RESET == TRUE
2997 #endif
2999 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
3001 #endif
3003 #if AGESA_ENTRY_INIT_EARLY == TRUE
3005 #endif
3007 #if AGESA_ENTRY_INIT_POST == TRUE
3009 #endif
3011 #if AGESA_ENTRY_INIT_ENV == TRUE
3013 #endif
3015 #if AGESA_ENTRY_INIT_MID == TRUE
3017 #endif
3019 #if AGESA_ENTRY_INIT_LATE == TRUE
3021 #endif
3023 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
3025 #endif
3027 #if AGESA_ENTRY_INIT_RESUME == TRUE
3029 #endif
3031 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
3033 #endif
3035 #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
3042 #endif
3044 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
3046 #endif
3048 };
3050 CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
3051 {
3052 IDS_LATE_RUN_AP_TASK
3053 // Get DMI info
3054 CPU_DMI_AP_GET_TYPE4_TYPE7
3055 // Probe filter enable
3056 L3_FEAT_AP_DISABLE_CACHE
3057 L3_FEAT_AP_ENABLE_CACHE
3058 // Cpu Late Init
3059 CPU_LATE_INIT_AP_TASK
3061 };
3063 #if AGESA_ENTRY_INIT_EARLY == TRUE
3064 #if IDSOPT_IDS_ENABLED == TRUE
3065 #if IDSOPT_TRACING_ENABLED == TRUE
3066 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
3068 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
3069 //Build Option Area
3077 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
3089 //Build Configuration Area
3090 // CoreVrm
3098 // NbVrm
3220 MAKE_DBG_STR (\nCfgDisplayMiscControl.VbiosFastBootEn , CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE),
3221 #endif
3222 NULL
3223 };
3224 #endif
3225 #endif
3226 #endif