2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
22 string "Local version string"
24 Append an extra string to the end of the coreboot version.
26 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
32 string "CBFS prefix to use"
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
38 config COMMON_CBFS_SPI_WRAPPER
44 Use common wrapper to interface CBFS to SPI bootrom.
46 config MULTIPLE_CBFS_INSTANCES
47 bool "Multiple CBFS instances in the bootrom"
50 Account for the firmware image containing more than one CBFS
51 instance. Locations of instances are known at build time and are
52 communicated between coreboot stages to make sure the next stage is
53 loaded from the appropriate instance.
56 prompt "Compiler to use"
59 This option allows you to select the compiler used for building
61 You must build the coreboot crosscompiler for the board that you
64 To build all the GCC crosscompilers (takes a LONG time), run:
67 For help on individual architectures, run the command:
73 Use the GNU Compiler Collection (GCC) to build coreboot.
75 For details see http://gcc.gnu.org.
77 config COMPILER_LLVM_CLANG
78 bool "LLVM/clang (TESTING ONLY - Not currently working)"
80 Use LLVM/clang to build coreboot. To use this, you must build the
81 coreboot version of the clang compiler. Run the command
83 Note that this option is not currently working correctly and should
84 really only be selected if you're trying to work on getting clang
87 For details see http://clang.llvm.org.
92 bool "Allow building with any toolchain"
94 depends on COMPILER_GCC
96 Many toolchains break when building coreboot since it uses quite
97 unusual linker features. Unless developers explicitely request it,
98 we'll have to assume that they use their distro compiler by mistake.
99 Make sure that using patched compilers is a conscious decision.
102 bool "Use ccache to speed up (re)compilation"
105 Enables the use of ccache for faster builds.
107 Requires the ccache utility in your system $PATH.
109 For details see https://ccache.samba.org.
112 bool "Generate flashmap descriptor parser using flex and bison"
115 Enable this option if you are working on the flashmap descriptor
116 parser and made changes to fmd_scanner.l or fmd_parser.y.
118 Otherwise, say N to use the provided pregenerated scanner/parser.
120 config SCONFIG_GENPARSER
121 bool "Generate SCONFIG parser using flex and bison"
124 Enable this option if you are working on the sconfig device tree
125 parser and made changes to sconfig.l or sconfig.y.
127 Otherwise, say N to use the provided pregenerated scanner/parser.
129 config USE_OPTION_TABLE
130 bool "Use CMOS for configuration values"
132 depends on HAVE_OPTION_TABLE
134 Enable this option if coreboot shall read options from the "CMOS"
135 NVRAM instead of using hard-coded values.
137 config STATIC_OPTION_TABLE
138 bool "Load default configuration values into CMOS on each boot"
140 depends on USE_OPTION_TABLE
142 Enable this option to reset "CMOS" NVRAM values to default on
143 every boot. Use this if you want the NVRAM configuration to
144 never be modified from its default values.
146 config UNCOMPRESSED_RAMSTAGE
150 config COMPRESS_RAMSTAGE
151 bool "Compress ramstage with LZMA"
152 default y if !UNCOMPRESSED_RAMSTAGE
155 Compress ramstage to save memory in the flash image. Note
156 that decompression might slow down booting if the boot flash
157 is connected through a slow link (i.e. SPI).
159 config COMPRESS_PRERAM_STAGES
160 bool "Compress romstage and verstage with LZ4"
164 Compress romstage and (if it exists) verstage with LZ4 to save flash
165 space and speed up boot, since the time for reading the image from SPI
166 (and in the vboot case verifying it) is usually much greater than the
167 time spent decompressing. Doesn't work for XIP stages (assume all
168 ARCH_X86 for now) for obvious reasons.
170 config INCLUDE_CONFIG_FILE
171 bool "Include the coreboot .config file into the ROM image"
174 Include the .config file that was used to compile coreboot
175 in the (CBFS) ROM image. This is useful if you want to know which
176 options were used to build a specific coreboot.rom image.
178 Saying Y here will increase the image size by 2-3KB.
180 You can use the following command to easily list the options:
182 grep -a CONFIG_ coreboot.rom
184 Alternatively, you can also use cbfstool to print the image
185 contents (including the raw 'config' item we're looking for).
189 $ cbfstool coreboot.rom print
190 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
194 Name Offset Type Size
195 cmos_layout.bin 0x0 cmos layout 1159
196 fallback/romstage 0x4c0 stage 339756
197 fallback/ramstage 0x53440 stage 186664
198 fallback/payload 0x80dc0 payload 51526
199 config 0x8d740 raw 3324
200 (empty) 0x8e480 null 3610440
202 config NO_XIP_EARLY_STAGES
204 default n if ARCH_X86
207 Identify if --xip parameter needs to be passed into cbfstool for early
210 config EARLY_CBMEM_INIT
211 def_bool !LATE_CBMEM_INIT
213 config COLLECT_TIMESTAMPS
214 bool "Create a table of timestamps collected during boot"
217 Make coreboot create a table of timer-ID/timer-value pairs to
218 allow measuring time spent at different phases of the boot process.
221 bool "Allow use of binary-only repository"
224 This draws in the blobs repository, which contains binary files that
225 might be required for some chipsets or boards.
226 This flag ensures that a "Free" option remains available for users.
229 bool "Code coverage support"
230 depends on COMPILER_GCC
233 Add code coverage support for coreboot. This will store code
234 coverage information in CBMEM for extraction from user space.
237 config RELOCATABLE_MODULES
241 If RELOCATABLE_MODULES is selected then support is enabled for
242 building relocatable modules in the RAM stage. Those modules can be
243 loaded anywhere and all the relocations are handled automatically.
245 config RELOCATABLE_RAMSTAGE
246 depends on EARLY_CBMEM_INIT
247 bool "Build the ramstage to be relocatable in 32-bit address space."
249 select RELOCATABLE_MODULES
251 The reloctable ramstage support allows for the ramstage to be built
252 as a relocatable module. The stage loader can identify a place
253 out of the OS way so that copying memory is unnecessary during an S3
254 wake. When selecting this option the romstage is responsible for
255 determing a stack location to use for loading the ramstage.
257 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
258 depends on RELOCATABLE_RAMSTAGE
259 bool "Cache the relocated ramstage outside of cbmem."
262 The relocated ramstage is saved in an area specified by the
263 by the board and/or chipset.
265 config NO_STAGE_CACHE
269 Do not save any component in stage cache for resume path. On resume,
270 all components would be read back from CBFS again.
272 config FLASHMAP_OFFSET
273 hex "Flash Map Offset"
274 default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
275 default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
276 default CBFS_SIZE if !ARCH_X86
279 Offset of flash map in firmware image
281 # TODO: This doesn't belong here, move to src/arch/x86/Kconfig
283 prompt "Bootblock behaviour"
284 default BOOTBLOCK_SIMPLE
286 config BOOTBLOCK_SIMPLE
287 bool "Always load fallback"
289 config BOOTBLOCK_NORMAL
290 bool "Switch to normal if CMOS says so"
294 # To be selected by arch, SoC or mainboard if it does not want use the normal
295 # src/lib/bootblock.c#main() C entry point.
296 config BOOTBLOCK_CUSTOM
300 config BOOTBLOCK_SOURCE
302 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
303 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
305 # To be selected by arch or platform if a C environment is available during the
306 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
307 config C_ENVIRONMENT_BOOTBLOCK
311 config SKIP_MAX_REBOOT_CNT_CLEAR
312 bool "Do not clear reboot count after successful boot"
314 depends on BOOTBLOCK_NORMAL
316 Do not clear the reboot count immediately after successful boot.
317 Set to allow the payload to control normal/fallback image recovery.
318 Note that it is the responsibility of the payload to reset the
319 normal boot bit to 1 after each successsful boot.
322 bool "Update existing coreboot.rom image"
325 If this option is enabled, no new coreboot.rom file
326 is created. Instead it is expected that there already
327 is a suitable file for further processing.
328 The bootblock will not be modified.
330 If unsure, select 'N'
332 config GENERIC_GPIO_LIB
336 If enabled, compile the generic GPIO library. A "generic" GPIO
337 implies configurability usually found on SoCs, particularly the
338 ability to control internal pull resistors.
344 Mainboards that can read a board ID from the hardware straps
345 (ie. GPIO) select this configuration option.
347 config BOARD_ID_MANUAL
350 depends on !BOARD_ID_AUTO
352 If you want to maintain a board ID, but the hardware does not
353 have straps to automatically determine the ID, you can say Y
354 here and add a file named 'board_id' to CBFS. If you don't know
355 what this is about, say N.
357 config BOARD_ID_STRING
360 depends on BOARD_ID_MANUAL
362 This string is placed in the 'board_id' CBFS file for indicating
365 config RAM_CODE_SUPPORT
369 If enabled, coreboot discovers RAM configuration (value obtained by
370 reading board straps) and stores it in coreboot table.
372 config BOOTSPLASH_IMAGE
373 bool "Add a bootsplash image"
375 Select this option if you have a bootsplash image that you would
376 like to add to your ROM.
378 This will only add the image to the ROM. To actually run it check
379 options under 'Display' section.
381 config BOOTSPLASH_FILE
382 string "Bootsplash path and filename"
383 depends on BOOTSPLASH_IMAGE
384 default "bootsplash.jpg"
386 The path and filename of the file to use as graphical bootsplash
387 screen. The file format has to be jpg.
391 source "src/acpi/Kconfig"
395 source "src/mainboard/Kconfig"
397 # defaults for CBFS_SIZE are set at the end of the file.
399 hex "Size of CBFS filesystem in ROM"
401 This is the part of the ROM actually managed by CBFS, located at the
402 end of the ROM (passed through cbfstool -o) on x86 and at at the start
403 of the ROM (passed through cbfstool -s) everywhere else. It defaults
404 to span the whole ROM on all but Intel systems that use an Intel Firmware
405 Descriptor. It can be overridden to make coreboot live alongside other
406 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
410 string "fmap description file in fmd format"
411 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
414 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
415 but in some cases more complex setups are required.
416 When an fmd is specified, it overrides the default format.
420 # load site-local kconfig to allow user specific defaults and overrides
421 source "site-local/Kconfig"
423 config SYSTEM_TYPE_LAPTOP
427 config CBFS_AUTOGEN_ATTRIBUTES
431 If this option is selected, every file in cbfs which has a constraint
432 regarding position or alignment will get an additional file attribute
433 which describes this constraint.
438 source "src/soc/*/*/Kconfig"
440 source "src/cpu/Kconfig"
441 comment "Northbridge"
442 source "src/northbridge/*/*/Kconfig"
443 comment "Southbridge"
444 source "src/southbridge/*/*/Kconfig"
446 source "src/superio/*/Kconfig"
447 comment "Embedded Controllers"
448 source "src/ec/acpi/Kconfig"
449 source "src/ec/*/*/Kconfig"
450 # FIXME move to vendorcode
451 source "src/drivers/intel/fsp1_0/Kconfig"
453 source "src/southbridge/intel/common/firmware/Kconfig"
454 source "src/vendorcode/*/Kconfig"
456 source "src/arch/*/Kconfig"
460 source "src/device/Kconfig"
462 menu "Generic Drivers"
463 source "src/drivers/*/Kconfig"
464 source "src/drivers/*/*/Kconfig"
474 select LPC_TPM if ARCH_X86
475 select I2C_TPM if ARCH_ARM
476 select I2C_TPM if ARCH_ARM64
478 Enable this option to enable TPM support in coreboot.
493 default 0x1000 if ARCH_X86
500 config MMCONF_SUPPORT_DEFAULT
504 config MMCONF_SUPPORT
508 config BOOTMODE_STRAPS
512 source "src/console/Kconfig"
514 config HAVE_ACPI_RESUME
518 config RESUME_PATH_SAME_AS_BOOT
520 default y if ARCH_X86
521 depends on HAVE_ACPI_RESUME
523 This option indicates that when a system resumes it takes the
524 same path as a regular boot. e.g. an x86 system runs from the
525 reset vector at 0xfffffff0 on both resume and warm/cold boot.
527 config HAVE_HARD_RESET
531 This variable specifies whether a given board has a hard_reset
532 function, no matter if it's provided by board code or chipset code.
534 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
538 config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
542 This should be enabled on certain plaforms, such as the AMD
543 SR565x, that cannot handle concurrent CBFS accesses from
544 multiple APs during early startup.
546 config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
550 config HAVE_MONOTONIC_TIMER
553 The board/chipset provides a monotonic timer.
555 config GENERIC_UDELAY
557 depends on HAVE_MONOTONIC_TIMER
559 The board/chipset uses a generic udelay function utilizing the
564 depends on HAVE_MONOTONIC_TIMER
566 Provide a timer queue for performing time-based callbacks.
568 config COOP_MULTITASKING
570 depends on TIMER_QUEUE && ARCH_X86
572 Cooperative multitasking allows callbacks to be multiplexed on the
573 main thread of ramstage. With this enabled it allows for multiple
574 execution paths to take place when they have udelay() calls within
580 depends on COOP_MULTITASKING
582 How many execution threads to cooperatively multitask with.
584 config HAVE_OPTION_TABLE
588 This variable specifies whether a given board has a cmos.layout
589 file containing NVRAM/CMOS bit definitions.
590 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
596 config HAVE_SMI_HANDLER
600 config PCI_IO_CFG_EXT
608 config CACHE_ROM_SIZE_OVERRIDE
612 # TODO: Can probably be removed once all chipsets have kconfig options for it.
617 config USE_WATCHDOG_ON_BOOT
625 Build board-specific VGA code.
631 Enable Unified Memory Architecture for graphics.
633 config HAVE_ACPI_TABLES
636 This variable specifies whether a given board has ACPI table support.
637 It is usually set in mainboard/*/Kconfig.
642 This variable specifies whether a given board has MP table support.
643 It is usually set in mainboard/*/Kconfig.
644 Whether or not the MP table is actually generated by coreboot
645 is configurable by the user via GENERATE_MP_TABLE.
647 config HAVE_PIRQ_TABLE
650 This variable specifies whether a given board has PIRQ table support.
651 It is usually set in mainboard/*/Kconfig.
652 Whether or not the PIRQ table is actually generated by coreboot
653 is configurable by the user via GENERATE_PIRQ_TABLE.
655 config MAX_PIRQ_LINKS
659 This variable specifies the number of PIRQ interrupt links which are
660 routable. On most chipsets, this is 4, INTA through INTD. Some
661 chipsets offer more than four links, commonly up to INTH. They may
662 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
663 table specifies links greater than 4, pirq_route_irqs will not
664 function properly, unless this variable is correctly set.
674 Build support for NHLT (non HD Audio) ACPI table generation.
676 #These Options are here to avoid "undefined" warnings.
677 #The actual selection and help texts are in the following menu.
681 config GENERATE_MP_TABLE
682 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
684 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
686 Generate an MP table (conforming to the Intel MultiProcessor
687 specification 1.4) for this board.
691 config GENERATE_PIRQ_TABLE
692 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
694 default HAVE_PIRQ_TABLE
696 Generate a PIRQ table for this board.
700 config GENERATE_SMBIOS_TABLES
702 bool "Generate SMBIOS tables"
705 Generate SMBIOS tables for this board.
709 config SMBIOS_PROVIDED_BY_MOBO
713 config MAINBOARD_SERIAL_NUMBER
714 string "SMBIOS Serial Number"
715 depends on GENERATE_SMBIOS_TABLES
716 depends on !SMBIOS_PROVIDED_BY_MOBO
719 The Serial Number to store in SMBIOS structures.
721 config MAINBOARD_VERSION
722 string "SMBIOS Version Number"
723 depends on GENERATE_SMBIOS_TABLES
724 depends on !SMBIOS_PROVIDED_BY_MOBO
727 The Version Number to store in SMBIOS structures.
729 config MAINBOARD_SMBIOS_MANUFACTURER
730 string "SMBIOS Manufacturer"
731 depends on GENERATE_SMBIOS_TABLES
732 depends on !SMBIOS_PROVIDED_BY_MOBO
733 default MAINBOARD_VENDOR
735 Override the default Manufacturer stored in SMBIOS structures.
737 config MAINBOARD_SMBIOS_PRODUCT_NAME
738 string "SMBIOS Product name"
739 depends on GENERATE_SMBIOS_TABLES
740 depends on !SMBIOS_PROVIDED_BY_MOBO
741 default MAINBOARD_PART_NUMBER
743 Override the default Product name stored in SMBIOS structures.
747 source "payloads/Kconfig"
751 # TODO: Better help text and detailed instructions.
753 bool "GDB debugging support"
755 depends on CONSOLE_SERIAL
757 If enabled, you will be able to set breakpoints for gdb debugging.
758 See src/arch/x86/lib/c_start.S for details.
761 bool "Wait for a GDB connection"
765 If enabled, coreboot will wait for a GDB connection.
768 bool "Halt when hitting a BUG() or assertion error"
771 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
774 bool "Output verbose CBFS debug messages"
777 This option enables additional CBFS related debug messages.
779 config HAVE_DEBUG_RAM_SETUP
782 config DEBUG_RAM_SETUP
783 bool "Output verbose RAM init debug messages"
785 depends on HAVE_DEBUG_RAM_SETUP
787 This option enables additional RAM init related debug messages.
788 It is recommended to enable this when debugging issues on your
789 board which might be RAM init related.
791 Note: This option will increase the size of the coreboot image.
795 config HAVE_DEBUG_CAR
800 depends on HAVE_DEBUG_CAR
802 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
803 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
804 # printk(BIOS_DEBUG, ...) calls.
806 bool "Output verbose Cache-as-RAM debug messages"
808 depends on HAVE_DEBUG_CAR
810 This option enables additional CAR related debug messages.
814 bool "Check PIRQ table consistency"
816 depends on GENERATE_PIRQ_TABLE
820 config HAVE_DEBUG_SMBUS
824 bool "Output verbose SMBus debug messages"
826 depends on HAVE_DEBUG_SMBUS
828 This option enables additional SMBus (and SPD) debug messages.
830 Note: This option will increase the size of the coreboot image.
835 bool "Output verbose SMI debug messages"
837 depends on HAVE_SMI_HANDLER
838 select SPI_FLASH_SMM if SPI_CONSOLE
840 This option enables additional SMI related debug messages.
842 Note: This option will increase the size of the coreboot image.
846 config DEBUG_SMM_RELOCATION
847 bool "Debug SMM relocation code"
849 depends on HAVE_SMI_HANDLER
851 This option enables additional SMM handler relocation related
854 Note: This option will increase the size of the coreboot image.
858 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
859 # printk(BIOS_DEBUG, ...) calls.
861 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
865 This option enables additional malloc related debug messages.
867 Note: This option will increase the size of the coreboot image.
871 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
872 # printk(BIOS_DEBUG, ...) calls.
874 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
878 This option enables additional ACPI related debug messages.
880 Note: This option will slightly increase the size of the coreboot image.
884 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
885 # printk(BIOS_DEBUG, ...) calls.
886 config REALMODE_DEBUG
887 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
890 depends on PCI_OPTION_ROM_RUN_REALMODE
892 This option enables additional x86emu related debug messages.
894 Note: This option will increase the time to emulate a ROM.
899 bool "Output verbose x86emu debug messages"
901 depends on PCI_OPTION_ROM_RUN_YABEL
903 This option enables additional x86emu related debug messages.
905 Note: This option will increase the size of the coreboot image.
909 config X86EMU_DEBUG_JMP
910 bool "Trace JMP/RETF"
912 depends on X86EMU_DEBUG
914 Print information about JMP and RETF opcodes from x86emu.
916 Note: This option will increase the size of the coreboot image.
920 config X86EMU_DEBUG_TRACE
921 bool "Trace all opcodes"
923 depends on X86EMU_DEBUG
925 Print _all_ opcodes that are executed by x86emu.
927 WARNING: This will produce a LOT of output and take a long time.
929 Note: This option will increase the size of the coreboot image.
933 config X86EMU_DEBUG_PNP
934 bool "Log Plug&Play accesses"
936 depends on X86EMU_DEBUG
938 Print Plug And Play accesses made by option ROMs.
940 Note: This option will increase the size of the coreboot image.
944 config X86EMU_DEBUG_DISK
947 depends on X86EMU_DEBUG
949 Print Disk I/O related messages.
951 Note: This option will increase the size of the coreboot image.
955 config X86EMU_DEBUG_PMM
958 depends on X86EMU_DEBUG
960 Print messages related to POST Memory Manager (PMM).
962 Note: This option will increase the size of the coreboot image.
967 config X86EMU_DEBUG_VBE
968 bool "Debug VESA BIOS Extensions"
970 depends on X86EMU_DEBUG
972 Print messages related to VESA BIOS Extension (VBE) functions.
974 Note: This option will increase the size of the coreboot image.
978 config X86EMU_DEBUG_INT10
979 bool "Redirect INT10 output to console"
981 depends on X86EMU_DEBUG
983 Let INT10 (i.e. character output) calls print messages to debug output.
985 Note: This option will increase the size of the coreboot image.
989 config X86EMU_DEBUG_INTERRUPTS
990 bool "Log intXX calls"
992 depends on X86EMU_DEBUG
994 Print messages related to interrupt handling.
996 Note: This option will increase the size of the coreboot image.
1000 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1001 bool "Log special memory accesses"
1003 depends on X86EMU_DEBUG
1005 Print messages related to accesses to certain areas of the virtual
1006 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1008 Note: This option will increase the size of the coreboot image.
1012 config X86EMU_DEBUG_MEM
1013 bool "Log all memory accesses"
1015 depends on X86EMU_DEBUG
1017 Print memory accesses made by option ROM.
1018 Note: This also includes accesses to fetch instructions.
1020 Note: This option will increase the size of the coreboot image.
1024 config X86EMU_DEBUG_IO
1025 bool "Log IO accesses"
1027 depends on X86EMU_DEBUG
1029 Print I/O accesses made by option ROM.
1031 Note: This option will increase the size of the coreboot image.
1035 config X86EMU_DEBUG_TIMINGS
1036 bool "Output timing information"
1038 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1040 Print timing information needed by i915tool.
1045 bool "Output verbose TPM debug messages"
1049 This option enables additional TPM related debug messages.
1051 config DEBUG_SPI_FLASH
1052 bool "Output verbose SPI flash debug messages"
1054 depends on SPI_FLASH
1056 This option enables additional SPI flash related debug messages.
1058 config DEBUG_USBDEBUG
1059 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1063 This option enables additional USB 2.0 debug dongle related messages.
1065 Select this to debug the connection of usbdebug dongle. Note that
1066 you need some other working console to receive the messages.
1068 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1069 # Only visible with the right southbridge and loglevel.
1070 config DEBUG_INTEL_ME
1071 bool "Verbose logging for Intel Management Engine"
1074 Enable verbose logging for Intel Management Engine driver that
1075 is present on Intel 6-series chipsets.
1079 bool "Trace function calls"
1082 If enabled, every function will print information to console once
1083 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1084 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1085 of calling function. Please note some printk related functions
1086 are omitted from trace to have good looking console dumps.
1088 config DEBUG_COVERAGE
1089 bool "Debug code coverage"
1093 If enabled, the code coverage hooks in coreboot will output some
1094 information about the coverage data that is dumped.
1098 # These probably belong somewhere else, but they are needed somewhere.
1099 config ENABLE_APIC_EXT_ID
1103 config WARNINGS_ARE_ERRORS
1107 # TODO: Remove this when all platforms are fixed.
1108 config IASL_WARNINGS_ARE_ERRORS
1111 Select to Fail the build if a IASL generates a warning.
1112 This will be defaulted to disabled for the platforms that
1113 currently fail. This allows the REST of the platforms to
1114 have this check enabled while we're working to get those
1117 DO NOT ADD TO ANY ADDITIONAL PLATFORMS INSTEAD OF FIXING
1120 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1121 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1122 # mutually exclusive. One of these options must be selected in the
1123 # mainboard Kconfig if the chipset supports enabling and disabling of
1124 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1125 # in mainboard/Kconfig to know if the button should be enabled or not.
1127 config POWER_BUTTON_DEFAULT_ENABLE
1130 Select when the board has a power button which can optionally be
1131 disabled by the user.
1133 config POWER_BUTTON_DEFAULT_DISABLE
1136 Select when the board has a power button which can optionally be
1137 enabled by the user, e.g. when the board ships with a jumper over
1138 the power switch contacts.
1140 config POWER_BUTTON_FORCE_ENABLE
1143 Select when the board requires that the power button is always
1146 config POWER_BUTTON_FORCE_DISABLE
1149 Select when the board requires that the power button is always
1150 disabled, e.g. when it has been hardwired to ground.
1152 config POWER_BUTTON_IS_OPTIONAL
1154 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1155 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1157 Internal option that controls ENABLE_POWER_BUTTON visibility.
1163 Internal option that controls whether we compile in register scripts.
1165 config MAX_REBOOT_CNT
1169 Internal option that sets the maximum number of bootblock executions allowed
1170 with the normal image enabled before assuming the normal image is defective
1171 and switching to the fallback image.
1177 This is the part of the ROM actually managed by CBFS. Set it to be
1178 equal to the full rom size if that hasn't been overridden by the
1179 chipset or mainboard.
1181 config DEBUG_BOOT_STATE
1185 Control debugging of the boot state machine. When selected displays
1186 the state boundaries in ramstage.