src/include/spi-generic.h

   1 /*
   2  * (C) Copyright 2001
   3  * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef _SPI_GENERIC_H_
  17 #define _SPI_GENERIC_H_
  18
  19 #include <commonlib/region.h>
  20 #include <stdint.h>
  21 #include <stddef.h>
  22
  23 /* Controller-specific definitions: */
  24
  25 struct spi_ctrlr;
  26
  27 /*-----------------------------------------------------------------------
  28  * Representation of a SPI slave, i.e. what we're communicating with.
  29  *
  30  *   bus:       ID of the bus that the slave is attached to.
  31  *   cs:        ID of the chip select connected to the slave.
  32  *   ctrlr:     Pointer to SPI controller structure.
  33  */
  34 struct spi_slave {
  35         unsigned int    bus;
  36         unsigned int    cs;
  37         const struct spi_ctrlr *ctrlr;
  38 };
  39
  40 /* Representation of SPI operation status. */
  41 enum spi_op_status {
  42         SPI_OP_NOT_EXECUTED = 0,
  43         SPI_OP_SUCCESS = 1,
  44         SPI_OP_FAILURE = 2,
  45 };
  46
  47 /*
  48  * Representation of a SPI operation.
  49  *
  50  * dout:        Pointer to data to send.
  51  * bytesout:    Count of data in bytes to send.
  52  * din: Pointer to store received data.
  53  * bytesin:     Count of data in bytes to receive.
  54  */
  55 struct spi_op {
  56         const void *dout;
  57         size_t bytesout;
  58         void *din;
  59         size_t bytesin;
  60         enum spi_op_status status;
  61 };
  62
  63 enum spi_clock_phase {
  64         SPI_CLOCK_PHASE_FIRST,
  65         SPI_CLOCK_PHASE_SECOND
  66 };
  67
  68 enum spi_wire_mode {
  69         SPI_4_WIRE_MODE,
  70         SPI_3_WIRE_MODE
  71 };
  72
  73 enum spi_polarity {
  74         SPI_POLARITY_LOW,
  75         SPI_POLARITY_HIGH
  76 };
  77
  78 struct spi_cfg {
  79         /* CLK phase - 0: Phase first, 1: Phase second */
  80         enum spi_clock_phase clk_phase;
  81         /* CLK polarity - 0: Low, 1: High */
  82         enum spi_polarity clk_polarity;
  83         /* CS polarity - 0: Low, 1: High */
  84         enum spi_polarity cs_polarity;
  85         /* Wire mode - 0: 4-wire, 1: 3-wire */
  86         enum spi_wire_mode wire_mode;
  87         /* Data bit length. */
  88         unsigned int data_bit_length;
  89 };
  90
  91 /*
  92  * If there is no limit on the maximum transfer size for the controller,
  93  * max_xfer_size can be set to SPI_CTRLR_DEFAULT_MAX_XFER_SIZE which is equal to
  94  * UINT32_MAX.
  95  */
  96 #define SPI_CTRLR_DEFAULT_MAX_XFER_SIZE (UINT32_MAX)
  97
  98 struct spi_flash;
  99
 100 enum {
 101         /* Deduct the command length from the spi_crop_chunk() calculation for
 102            sizing a transaction. */
 103         SPI_CNTRLR_DEDUCT_CMD_LEN = 1 << 0,
 104         /* Remove the opcode size from the command length used in the
 105            spi_crop_chunk() calculation. Controllers which have a dedicated
 106            register for the command byte would set this flag which would
 107            allow the use of the maximum transfer size. */
 108         SPI_CNTRLR_DEDUCT_OPCODE_LEN = 1 << 1,
 109 };
 110
 111 /*-----------------------------------------------------------------------
 112  * Representation of a SPI controller. Note the xfer() and xfer_vector()
 113  * callbacks are meant to process full duplex transactions. If the
 114  * controller cannot handle these transactions then return an error when
 115  * din and dout are both set. See spi_xfer() below for more details.
 116  *
 117  * claim_bus:           Claim SPI bus and prepare for communication.
 118  * release_bus: Release SPI bus.
 119  * setup:               Setup given SPI device bus.
 120  * xfer:                Perform one SPI transfer operation.
 121  * xfer_vector: Vector of SPI transfer operations.
 122  * max_xfer_size:       Maximum transfer size supported by the controller
 123  *                      (0 = invalid,
 124  *                       SPI_CTRLR_DEFAULT_MAX_XFER_SIZE = unlimited)
 125  * flags:               See SPI_CNTRLR_* enums above.
 126  *
 127  * Following member is provided by specialized SPI controllers that are
 128  * actually SPI flash controllers.
 129  *
 130  * flash_probe: Specialized probe function provided by SPI flash
 131  *                      controllers.
 132  * flash_protect: Protect a region of flash using the SPI flash controller.
 133  */
 134 struct spi_ctrlr {
 135         int (*claim_bus)(const struct spi_slave *slave);
 136         void (*release_bus)(const struct spi_slave *slave);
 137         int (*setup)(const struct spi_slave *slave);
 138         int (*xfer)(const struct spi_slave *slave, const void *dout,
 139                     size_t bytesout, void *din, size_t bytesin);
 140         int (*xfer_vector)(const struct spi_slave *slave,
 141                         struct spi_op vectors[], size_t count);
 142         uint32_t max_xfer_size;
 143         uint32_t flags;
 144         int (*flash_probe)(const struct spi_slave *slave,
 145                                 struct spi_flash *flash);
 146         int (*flash_protect)(const struct spi_flash *flash,
 147                                 const struct region *region);
 148 };
 149
 150 /*-----------------------------------------------------------------------
 151  * Structure defining mapping of SPI buses to controller.
 152  *
 153  * ctrlr:       Pointer to controller structure managing the given SPI buses.
 154  * bus_start:   Start bus number managed by the controller.
 155  * bus_end:     End bus number manager by the controller.
 156  */
 157 struct spi_ctrlr_buses {
 158         const struct spi_ctrlr *ctrlr;
 159         unsigned int bus_start;
 160         unsigned int bus_end;
 161 };
 162
 163 /* Mapping of SPI buses to controllers - should be defined by platform. */
 164 extern const struct spi_ctrlr_buses spi_ctrlr_bus_map[];
 165 extern const size_t spi_ctrlr_bus_map_count;
 166
 167 /*-----------------------------------------------------------------------
 168  * Initialization, must be called once on start up.
 169  *
 170  */
 171 void spi_init(void);
 172
 173 /*
 174  * Get configuration of SPI bus.
 175  *
 176  * slave:     Pointer to slave structure.
 177  * cfg:       Pointer to SPI configuration that needs to be filled.
 178  *
 179  * Returns:
 180  * 0 on success, -1 on error
 181  */
 182 int spi_get_config(const struct spi_slave *slave, struct spi_cfg *cfg);
 183
 184 /*-----------------------------------------------------------------------
 185  * Set up communications parameters for a SPI slave.
 186  *
 187  * This must be called once for each slave. Note that this function
 188  * usually doesn't touch any actual hardware, it only initializes the
 189  * contents of spi_slave so that the hardware can be easily
 190  * initialized later.
 191  *
 192  *   bus:     Bus ID of the slave chip.
 193  *   cs:      Chip select ID of the slave chip on the specified bus.
 194  *   slave:   Pointer to slave structure that needs to be initialized.
 195  *
 196  * Returns:
 197  * 0 on success, -1 on error
 198  */
 199 int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave);
 200
 201 /*-----------------------------------------------------------------------
 202  * Claim the bus and prepare it for communication with a given slave.
 203  *
 204  * This must be called before doing any transfers with a SPI slave. It
 205  * will enable and initialize any SPI hardware as necessary, and make
 206  * sure that the SCK line is in the correct idle state. It is not
 207  * allowed to claim the same bus for several slaves without releasing
 208  * the bus in between.
 209  *
 210  *   slave:     The SPI slave
 211  *
 212  * Returns: 0 if the bus was claimed successfully, or a negative value
 213  * if it wasn't.
 214  */
 215 int spi_claim_bus(const struct spi_slave *slave);
 216
 217 /*-----------------------------------------------------------------------
 218  * Release the SPI bus
 219  *
 220  * This must be called once for every call to spi_claim_bus() after
 221  * all transfers have finished. It may disable any SPI hardware as
 222  * appropriate.
 223  *
 224  *   slave:     The SPI slave
 225  */
 226 void spi_release_bus(const struct spi_slave *slave);
 227
 228 /*-----------------------------------------------------------------------
 229  * SPI transfer
 230  *
 231  * spi_xfer() interface:
 232  *   slave:     The SPI slave which will be sending/receiving the data.
 233  *   dout:      Pointer to a string of bytes to send out.
 234  *   bytesout:  How many bytes to write.
 235  *   din:       Pointer to a string of bytes that will be filled in.
 236  *   bytesin:   How many bytes to read.
 237  *
 238  * Note that din and dout are transferred simulataneously in a full duplex
 239  * transaction. The number of clocks within one transaction is calculated
 240  * as: MAX(bytesout*8, bytesin*8).
 241  *
 242  *   Returns: 0 on success, not 0 on failure
 243  */
 244 int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout,
 245              void *din, size_t bytesin);
 246
 247 /*-----------------------------------------------------------------------
 248  * Vector of SPI transfer operations
 249  *
 250  * spi_xfer_vector() interface:
 251  *   slave:     The SPI slave which will be sending/receiving the data.
 252  *   vectors:   Array of SPI op structures.
 253  *   count:     Number of SPI op vectors.
 254  *
 255  *   Returns: 0 on success, not 0 on failure
 256  */
 257 int spi_xfer_vector(const struct spi_slave *slave,
 258                 struct spi_op vectors[], size_t count);
 259
 260 /*-----------------------------------------------------------------------
 261  * Given command length and length of remaining data, return the maximum data
 262  * that can be transferred in next spi_xfer.
 263  *
 264  * Returns: 0 on error, non-zero data size that can be xfered on success.
 265  */
 266 unsigned int spi_crop_chunk(const struct spi_slave *slave, unsigned int cmd_len,
 267                         unsigned int buf_len);
 268
 269 /*-----------------------------------------------------------------------
 270  * Write 8 bits, then read 8 bits.
 271  *   slave:     The SPI slave we're communicating with
 272  *   byte:      Byte to be written
 273  *
 274  * Returns: The value that was read, or a negative value on error.
 275  *
 276  * TODO: This function probably shouldn't be inlined.
 277  */
 278 static inline int spi_w8r8(const struct spi_slave *slave, unsigned char byte)
 279 {
 280         unsigned char dout[2];
 281         unsigned char din[2];
 282         int ret;
 283
 284         dout[0] = byte;
 285         dout[1] = 0;
 286
 287         ret = spi_xfer(slave, dout, 2, din, 2);
 288         return ret < 0 ? ret : din[1];
 289 }
 290
 291 #endif  /* _SPI_GENERIC_H_ */