src/include/spd_ddr2.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2007-2009 coresystems GmbH
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef __SPD_DDR2_H__
  18 #define __SPD_DDR2_H__
  19
  20 /* SPDs for DDR2 SDRAM */
  21 #define SPD_MEM_TYPE    2
  22         #define SPD_MEM_TYPE_SDRAM_DDR  0x07
  23         #define SPD_MEM_TYPE_SDRAM_DDR2 0x08
  24
  25 #define SPD_DIMM_TYPE   20      /* x  bit0 or bit4 =1 mean registered*/
  26         #define SPD_DIMM_TYPE_RDIMM     0x01
  27         #define SPD_DIMM_TYPE_UDIMM     0x02
  28         #define SPD_DIMM_TYPE_SODIMM    0x04
  29         #define SPD_72B_SO_CDIMM        0x06
  30         #define SPD_72B_SO_RDIMM        0x07
  31         #define SPD_DIMM_TYPE_uDIMM     0x08
  32         #define SPD_DIMM_TYPE_mRDIMM    0x10
  33         #define SPD_DIMM_TYPE_mUDIMM    0x20
  34
  35 #define SPD_MOD_ATTRIB  21
  36         #define SPD_MOD_ATTRIB_DIFCK    0x20
  37         #define SPD_MOD_ATTRIB_REGADC   0x11   /* x */
  38         #define SPD_MOD_ATTRIB_PROBE    0x40
  39
  40 #define SPD_DEV_ATTRIB  22  /* Device attributes --- general */
  41 #define SPD_DIMM_CONF_TYPE      11
  42         #define SPD_DIMM_CONF_TYPE_ECC          0x02
  43         #define SPD_DIMM_CONF_TYPE_ADDR_PARITY  0x04     /* ? */
  44
  45 #define SPD_CAS_LAT_MIN_X_1     23
  46 #define SPD_CAS_LAT_MAX_X_1     24
  47 #define SPD_CAS_LAT_MIN_X_2     25
  48 #define SPD_CAS_LAT_MAX_X_2     26
  49
  50 #define SPD_BURST_LENGTHS       16
  51         #define SPD_BURST_LENGTHS_4     (1<<2)
  52         #define SPD_BURST_LENGTHS_8     (1<<3)
  53
  54 #define SPD_ROW_NUM     3       /* Number of Row addresses */
  55 #define SPD_COL_NUM     4       /* Number of Column addresses */
  56 #define SPD_BANK_NUM    17      /* SDRAM Device attributes - Number of Banks on
  57                                  SDRAM device, it could be 0x4, 0x8, so address
  58                                  lines for that would be 2, and 3 */
  59
  60 /* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planr),
  61  * Height bit[7:5]
  62  */
  63 #define SPD_MOD_ATTRIB_RANK     5
  64         #define SPD_MOD_ATTRIB_RANK_NUM_SHIFT   0
  65         #define SPD_MOD_ATTRIB_RANK_NUM_MASK    0x07
  66                 #define SPD_MOD_ATTRIB_RANK_NUM_BASE    1
  67                 #define SPD_MOD_ATTRIB_RANK_NUM_MIN     1
  68                 #define SPD_MOD_ATTRIB_RANK_NUM_MAX     8
  69
  70 #define SPD_RANK_SIZE   31      /* Only one bit is set */
  71         #define SPD_RANK_SIZE_1GB       (1<<0)
  72         #define SPD_RANK_SIZE_2GB       (1<<1)
  73         #define SPD_RANK_SIZE_4GB       (1<<2)
  74         #define SPD_RANK_SIZE_8GB       (1<<3)
  75         #define SPD_RANK_SIZE_16GB      (1<<4)
  76         #define SPD_RANK_SIZE_128MB     (1<<5)
  77         #define SPD_RANK_SIZE_256MB     (1<<6)
  78         #define SPD_RANK_SIZE_512MB     (1<<7)
  79
  80 /* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */
  81 #define SPD_DATA_WIDTH          6
  82 /* Primary SDRAM Width, it could be 0x08 or 0x10 */
  83 #define SPD_PRI_WIDTH           13
  84 /* Error Checking SDRAM Width, it could be 0x08 or 0x10 */
  85 #define SPD_ERR_WIDTH           14
  86
  87 #define SPD_CAS_LAT     18      /* SDRAM Device Attributes -- CAS Latency */
  88         #define SPD_CAS_LAT_2   (1<<2)
  89         #define SPD_CAS_LAT_3   (1<<3)
  90         #define SPD_CAS_LAT_4   (1<<4)
  91         #define SPD_CAS_LAT_5   (1<<5)
  92         #define SPD_CAS_LAT_6   (1<<6)
  93         #define SPD_CAS_LAT_7   (1<<7)
  94
  95 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2)
  96  *      + (val & 3) * 0.25)ns
  97  */
  98 #define SPD_TRP         27
  99 #define SPD_TRRD        28
 100 #define SPD_TRCD        29
 101 #define SPD_TRAS        30
 102 #define SPD_TWR         36      /* x */
 103 #define SPD_TWTR        37      /* x */
 104 #define SPD_TRTP        38      /* x */
 105
 106 #define SPD_EX_TRC_TRFC 40
 107 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)]
 108  *      ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}
 109  */
 110 #define SPD_TRC         41
 111 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)]
 112  *      + (val40 & 1)*256
 113  */
 114 #define SPD_TRFC        42
 115
 116 #define SPD_TREF        12
 117
 118 #endif /* __SPD_DDR2_H__ */