20 config RISCV_CODEMODEL
23 config ARCH_RISCV_M_DISABLED
27 # Whether a SOC implements M mode.
28 # M mode is the most privileged mode, it is
29 # the equivalent in some ways of x86 SMM mode
30 # save that in M mode it is impossible to turn
32 # While the spec requires it, there is at least
33 # one implementation that will not have it due
34 # to security concerns.
36 default y if ARCH_RISCV && !ARCH_RISCV_M_DISABLED
40 # S (supervisor) mode is for kernels. It is optional.
44 config RISCV_HAS_OPENSBI
48 bool "Use OpenSBI to hand over control to payload"
49 depends on ARCH_RISCV_M && ARCH_RISCV_S
50 depends on RISCV_HAS_OPENSBI
53 Load OpenSBI after payload has been loaded and use it to
54 provide the SBI and to handover control to payload.
56 config OPENSBI_PLATFORM
58 depends on RISCV_HAS_OPENSBI
60 The OpenSBI platform to build for.
62 config OPENSBI_TEXT_START
64 depends on RISCV_HAS_OPENSBI
66 The linking address used to build opensbi.
69 # U (user) mode is for programs.
77 config ARCH_BOOTBLOCK_RISCV
81 config ARCH_VERSTAGE_RISCV
85 config ARCH_ROMSTAGE_RISCV
89 config ARCH_RAMSTAGE_RISCV
93 config RISCV_USE_ARCH_TIMER
97 config RISCV_WORKING_HARTID
100 endif # if ARCH_RISCV