src/soc/intel/fsp_broadwell_de/southcluster.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2013 Google Inc.
   6  * Copyright (C) 2015-2016 Intel Corp.
   7  * Copyright (C) 2017 Siemens AG
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <stdint.h>
  20 #include <arch/io.h>
  21 #include <arch/ioapic.h>
  22 #include <console/console.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include <device/pci_def.h>
  27 #include <pc80/mc146818rtc.h>
  28 #include <pc80/i8254.h>
  29 #include <pc80/i8259.h>
  30 #include <pc80/isa-dma.h>
  31 #include <romstage_handoff.h>
  32 #include <soc/iomap.h>
  33 #include <soc/irq.h>
  34 #include <soc/lpc.h>
  35 #include <soc/pci_devs.h>
  36 #include <soc/ramstage.h>
  37 #include <chip.h>
  38
  39 typedef struct soc_intel_fsp_broadwell_de_config config_t;
  40
  41 static inline void
  42 add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
  43 {
  44         mmio_resource(dev, i, addr >> 10, size >> 10);
  45 }
  46
  47 static void sc_add_mmio_resources(device_t dev)
  48 {
  49         add_mmio_resource(dev, 0xfeb0,
  50                                ABORT_BASE_ADDRESS,
  51                                ABORT_BASE_SIZE);
  52         add_mmio_resource(dev, 0xfeb8,
  53                                PSEG_BASE_ADDRESS,
  54                                PSEG_BASE_SIZE);
  55         add_mmio_resource(dev, 0xfec0,
  56                                IOXAPIC1_BASE_ADDRESS,
  57                                IOXAPIC1_BASE_SIZE);
  58         add_mmio_resource(dev, 0xfec1,
  59                                IOXAPIC2_BASE_ADDRESS,
  60                                IOXAPIC2_BASE_SIZE);
  61         add_mmio_resource(dev, 0xfed0,
  62                                PCH_BASE_ADDRESS,
  63                                PCH_BASE_SIZE);
  64         add_mmio_resource(dev, 0xfee0,
  65                                LXAPIC_BASE_ADDRESS,
  66                                LXAPIC_BASE_SIZE);
  67         add_mmio_resource(dev, 0xff00,
  68                                FIRMWARE_BASE_ADDRESS,
  69                                FIRMWARE_BASE_SIZE);
  70 }
  71
  72 /*
  73  * Write PCI config space IRQ assignments.  PCI devices have the INT_LINE
  74  * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing
  75  * information to operating systems and drivers.  The INT_PIN register is
  76  * generally read only and reports which interrupt pin A - D it uses.  The
  77  * INT_LINE register is configurable and reports which IRQ (generally the
  78  * PIC IRQs 1 - 15) it will use.  This needs to take interrupt pin swizzling
  79  * on devices that are downstream on a PCI bridge into account.
  80  *
  81  * This function will loop through all enabled PCI devices and program the
  82  * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it
  83  * uses.  It then configures each interrupt in the pic to be level triggered.
  84  */
  85 static void write_pci_config_irqs(void)
  86 {
  87         device_t irq_dev;
  88         device_t targ_dev;
  89         uint8_t int_line = 0;
  90         uint8_t original_int_pin = 0;
  91         uint8_t new_int_pin = 0;
  92         uint16_t current_bdf = 0;
  93         uint16_t parent_bdf = 0;
  94         uint8_t pirq = 0;
  95         uint8_t device_num = 0;
  96         const struct broadwell_de_irq_route *ir = &global_broadwell_de_irq_route;
  97
  98         if (ir == NULL) {
  99                 printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because"
 100                                 " 'global_broadwell_de_irq_route' structure does not exist\n");
 101                 return;
 102         }
 103
 104         /*
 105          * Loop through all enabled devices and program their
 106          * INT_LINE, INT_PIN registers from values taken from
 107          * the Interrupt Route registers in the ILB
 108          */
 109         printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
 110         for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 111
 112                 if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
 113                         (!irq_dev->enabled))
 114                         continue;
 115
 116                 current_bdf = irq_dev->path.pci.devfn |
 117                         irq_dev->bus->secondary << 8;
 118
 119                 /*
 120                  * Step 1: Get the INT_PIN and device structure to look for
 121                  * in the pirq_data table defined in the mainboard directory.
 122                  */
 123                 targ_dev = NULL;
 124                 new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev);
 125                 if (targ_dev == NULL || new_int_pin < 1)
 126                         continue;
 127
 128                 /* Get the original INT_PIN for record keeping */
 129                 original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
 130
 131                 parent_bdf = targ_dev->path.pci.devfn
 132                         | targ_dev->bus->secondary << 8;
 133                 device_num = PCI_SLOT(parent_bdf);
 134
 135                 if (ir->pcidev[device_num] == 0) {
 136                         printk(BIOS_WARNING,
 137                                 "Warning: PCI Device %d does not have an IRQ entry, skipping it\n",
 138                                 device_num);
 139                         continue;
 140                 }
 141
 142                 /* Find the PIRQ that is attached to the INT_PIN this device uses */
 143                 pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF;
 144
 145                 /* Get the INT_LINE this device/function will use */
 146                 int_line = ir->pic[pirq];
 147
 148                 if (int_line != PIRQ_PIC_IRQDISABLE) {
 149                         /* Set this IRQ to level triggered since it is used by a PCI device */
 150                         i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED);
 151                         /* Set the Interrupt Line register in PCI config space */
 152                         pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
 153                 } else {
 154                         /* Set the Interrupt line register as "unknown or unused" */
 155                         pci_write_config8(irq_dev, PCI_INTERRUPT_LINE,
 156                                 PIRQ_PIC_UNKNOWN_UNUSED);
 157                 }
 158
 159                 printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n",
 160                         original_int_pin, pin_to_str(original_int_pin));
 161                 if (parent_bdf != current_bdf)
 162                         printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n",
 163                                                         new_int_pin, pin_to_str(new_int_pin));
 164                 printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n"
 165                                                 "\tINT_LINE\t: 0x%X (IRQ %d)\n",
 166                                                 'A' + pirq, int_line, int_line);
 167         }
 168         printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
 169 }
 170
 171 static void sc_pirq_init(device_t dev)
 172 {
 173         int i;
 174         const uint8_t *pirq = global_broadwell_de_irq_route.pic;
 175         printk(BIOS_DEBUG, "Programming PIRQ[A-H] Routing Control Register\n");
 176
 177         for (i = 0; i < 8; i++) {
 178                 pci_write_config8(dev, (i < 4) ? (PIRQ_RCR1+i) : (PIRQ_RCR2+i-4), pirq[i]);
 179                 printk(BIOS_DEBUG, "  PIRQ[%c]: %.2x\n"
 180                         , 'A'+i
 181                         , pci_read_config8(dev, (i < 4) ? (PIRQ_RCR1+i) : (PIRQ_RCR2+i-4))
 182                         );
 183         }
 184 }
 185
 186 static void sc_add_io_resources(device_t dev)
 187 {
 188         struct resource *res;
 189         u8 io_index = 0;
 190
 191         /*
 192          * Add the default claimed IO range for the LPC device
 193          * and mark it as subtractive decode.
 194          */
 195         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 196         res->base = LPC_DEFAULT_IO_RANGE_LOWER;
 197         res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
 198         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 199                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 200
 201         /* Add the resource for GPIOs */
 202         res = new_resource(dev, GPIO_BASE_ADR_OFFSET);
 203         res->base = GPIO_BASE_ADDRESS;
 204         res->size = GPIO_BASE_SIZE;
 205         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 206         /* There is a separated enable-bit in GPIO_CTRL-register. It was set
 207          * already in romstage but FSP was active in the meantime and could have
 208          * cleared it. Set it here again to enable allocated IO-space for sure.
 209          */
 210         pci_write_config8(dev, GPIO_CTRL_OFFSET, GPIO_DECODE_ENABLE);
 211 }
 212
 213 static void sc_read_resources(device_t dev)
 214 {
 215         pci_dev_read_resources(dev);
 216         sc_add_mmio_resources(dev);
 217         sc_add_io_resources(dev);
 218 }
 219
 220 static void sc_init(struct device *dev)
 221 {
 222         printk(BIOS_DEBUG, "soc: southcluster_init\n");
 223
 224         /* Set the value for PCI command register. */
 225         pci_write_config16(dev, PCI_COMMAND,
 226                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 227                 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 228
 229         /* Program Serial IRQ register. */
 230         pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_CONT);
 231         if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) {
 232                 /* If SERIRQ have to operate in quiet mode, it should have been
 233                    run in continuous mode for at least one frame first. Use I/O
 234                    access to achieve the delay of at least one LPC cycle. */
 235                 outb(inb(0x80), 0x80);
 236                 pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_QUIET);
 237         }
 238
 239         sc_pirq_init(dev);
 240         write_pci_config_irqs();
 241         isa_dma_init();
 242         setup_i8259();
 243         setup_i8254();
 244 }
 245
 246 /*
 247  * Common code for the south cluster devices.
 248  */
 249 void southcluster_enable_dev(device_t dev)
 250 {
 251         uint32_t reg32;
 252
 253         if (!dev->enabled) {
 254                 int slot = PCI_SLOT(dev->path.pci.devfn);
 255                 int func = PCI_FUNC(dev->path.pci.devfn);
 256                 printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n",
 257                        dev_path(dev), slot, func);
 258
 259                 /* Ensure memory, io, and bus master are all disabled */
 260                 reg32 = pci_read_config32(dev, PCI_COMMAND);
 261                 reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 262                 pci_write_config32(dev, PCI_COMMAND, reg32);
 263         }
 264 }
 265
 266 static struct device_operations device_ops = {
 267         .read_resources   = sc_read_resources,
 268         .set_resources    = pci_dev_set_resources,
 269         .enable_resources = NULL,
 270         .init             = sc_init,
 271         .enable           = southcluster_enable_dev,
 272         .scan_bus         = scan_lpc_bus,
 273         .ops_pci          = &soc_pci_ops,
 274 };
 275
 276 static const struct pci_driver southcluster __pci_driver = {
 277         .ops    = &device_ops,
 278         .vendor = PCI_VENDOR_ID_INTEL,
 279         .device = LPC_DEVID,
 280 };
 281
 282 static const struct pci_driver southcluster_es2 __pci_driver = {
 283         .ops    = &device_ops,
 284         .vendor = PCI_VENDOR_ID_INTEL,
 285         .device = LPC_DEVID_ES2,
 286 };