?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sb/intel: Factor out soc_fill_gnvs()
[coreboot.git] / src / soc / intel / broadwell / pch / lpc.c
blob7c6cf8268dc9617f57d87738aad295fd7db2bcb2
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <option.h>
8 #include <pc80/isa-dma.h>
9 #include <pc80/i8259.h>
10 #include <device/pci_ops.h>
11 #include <arch/ioapic.h>
12 #include <acpi/acpi.h>
13 #include <acpi/acpi_gnvs.h>
14 #include <cpu/x86/smm.h>
15 #include <string.h>
16 #include <soc/gpio.h>
17 #include <soc/iobp.h>
18 #include <soc/iomap.h>
19 #include <soc/lpc.h>
20 #include <soc/nvs.h>
21 #include <soc/pch.h>
22 #include <soc/pci_devs.h>
23 #include <soc/pm.h>
24 #include <soc/ramstage.h>
25 #include <soc/rcba.h>
26 #include <soc/intel/broadwell/pch/chip.h>
27 #include <acpi/acpigen.h>
28 #include <southbridge/intel/common/rtc.h>
29
30 static void pch_enable_ioapic(struct device *dev)
31 {
32 u32 reg32;
33
34 /* Assign unique bus/dev/fn for I/O APIC */
35 pci_write_config16(dev, LPC_IBDF,
36 PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
37
38 set_ioapic_id(VIO_APIC_VADDR, 0x02);
39
40 /* affirm full set of redirection table entries ("write once") */
41 reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
42
43 /* PCH-LP has 39 redirection entries */
44 reg32 &= ~0x00ff0000;
45 reg32 |= 0x00270000;
46
47 io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
48
49 /*
50 * Select Boot Configuration register (0x03) and
51 * use Processor System Bus (0x01) to deliver interrupts.
52 */
53 io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
54 }
55
56 static void enable_hpet(struct device *dev)
57 {
58 size_t i;
59
60 /* Assign unique bus/dev/fn for each HPET */
61 for (i = 0; i < 8; ++i)
62 pci_write_config16(dev, LPC_HnBDF(i),
63 PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
64 }
65
66 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
67 * 0x00 - 0000 = Reserved
68 * 0x01 - 0001 = Reserved
69 * 0x02 - 0010 = Reserved
70 * 0x03 - 0011 = IRQ3
71 * 0x04 - 0100 = IRQ4
72 * 0x05 - 0101 = IRQ5
73 * 0x06 - 0110 = IRQ6
74 * 0x07 - 0111 = IRQ7
75 * 0x08 - 1000 = Reserved
76 * 0x09 - 1001 = IRQ9
77 * 0x0A - 1010 = IRQ10
78 * 0x0B - 1011 = IRQ11
79 * 0x0C - 1100 = IRQ12
80 * 0x0D - 1101 = Reserved
81 * 0x0E - 1110 = IRQ14
82 * 0x0F - 1111 = IRQ15
83 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
84 * 0x80 - The PIRQ is not routed.
85 */
86
87 static void pch_pirq_init(struct device *dev)
88 {
89 struct device *irq_dev;
90
91 const uint8_t pirq = 0x80;
92
93 pci_write_config8(dev, PIRQA_ROUT, pirq);
94 pci_write_config8(dev, PIRQB_ROUT, pirq);
95 pci_write_config8(dev, PIRQC_ROUT, pirq);
96 pci_write_config8(dev, PIRQD_ROUT, pirq);
97
98 pci_write_config8(dev, PIRQE_ROUT, pirq);
99 pci_write_config8(dev, PIRQF_ROUT, pirq);
100 pci_write_config8(dev, PIRQG_ROUT, pirq);
101 pci_write_config8(dev, PIRQH_ROUT, pirq);
102
103 for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
104 u8 int_pin = 0, int_line = 0;
105
106 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
107 continue;
108
109 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
110
111 switch (int_pin) {
112 case 1: /* INTA# */
113 case 2: /* INTB# */
114 case 3: /* INTC# */
115 case 4: /* INTD# */
116 int_line = pirq;
117 break;
118 }
119
120 if (!int_line)
121 continue;
122
123 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
124 }
125 }
126
127 static void pch_power_options(struct device *dev)
128 {
129 u16 reg16;
130 const char *state;
131 /* Get the chip configuration */
132 const struct soc_intel_broadwell_pch_config *config = config_of(dev);
133 int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
134
135 /* Which state do we want to goto after g3 (power restored)?
136 * 0 == S0 Full On
137 * 1 == S5 Soft Off
138 *
139 * If the option is not existent (Laptops), use Kconfig setting.
140 */
141 get_option(&pwr_on, "power_on_after_fail");
142
143 reg16 = pci_read_config16(dev, GEN_PMCON_3);
144 reg16 &= 0xfffe;
145 switch (pwr_on) {
146 case MAINBOARD_POWER_OFF:
147 reg16 |= 1;
148 state = "off";
149 break;
150 case MAINBOARD_POWER_ON:
151 reg16 &= ~1;
152 state = "on";
153 break;
154 case MAINBOARD_POWER_KEEP:
155 reg16 &= ~1;
156 state = "state keep";
157 break;
158 default:
159 state = "undefined";
160 }
161 pci_write_config16(dev, GEN_PMCON_3, reg16);
162 printk(BIOS_INFO, "Set power %s after power failure.\n", state);
163
164 /* GPE setup based on device tree configuration */
165 enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
166 config->gpe0_en_3, config->gpe0_en_4);
167
168 /* SMI setup based on device tree configuration */
169 enable_alt_smi(config->alt_gp_smi_en);
170 }
171
172 static void pch_misc_init(struct device *dev)
173 {
174 u8 reg8;
175 u16 reg16;
176 u32 reg32;
177
178 reg16 = pci_read_config16(dev, GEN_PMCON_3);
179
180 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
181 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
182
183 reg16 &= ~(1 << 10);
184 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
185
186 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
187
188 pci_write_config16(dev, GEN_PMCON_3, reg16);
189
190 /* Prepare sleep mode */
191 reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
192 reg32 &= ~SLP_TYP;
193 reg32 |= SCI_EN;
194 outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT);
195
196 /* Set up NMI on errors */
197 reg8 = inb(0x61);
198 reg8 &= ~0xf0; /* Higher nibble must be 0 */
199 reg8 |= (1 << 2); /* PCI SERR# disable for now */
200 outb(reg8, 0x61);
201
202 /* Disable NMI sources */
203 reg8 = inb(0x70);
204 reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
205 outb(reg8, 0x70);
206
207 /* Indicate DRAM init done for MRC */
208 pci_or_config8(dev, GEN_PMCON_2, 1 << 7);
209
210 /* Enable BIOS updates outside of SMM */
211 pci_and_config8(dev, BIOS_CNTL, ~(1 << 5));
212
213 /* Clear status bits to prevent unexpected wake */
214 RCBA32_OR(0x3310, 0x2f);
215
216 RCBA32_AND_OR(0x3f02, ~0xf, 0);
217
218 /* Enable PCIe Releaxed Order */
219 RCBA32_OR(0x2314, (1 << 31) | (1 << 7)),
220 RCBA32_OR(0x1114, (1 << 15) | (1 << 14)),
221
222 /* Setup SERIRQ, enable continuous mode */
223 reg8 = pci_read_config8(dev, SERIRQ_CNTL);
224 reg8 |= 1 << 7;
225
226 if (CONFIG(SERIRQ_CONTINUOUS_MODE))
227 reg8 |= 1 << 6;
228
229 pci_write_config8(dev, SERIRQ_CNTL, reg8);
230 }
231
232 /* Magic register settings for power management */
233 static void pch_pm_init_magic(struct device *dev)
234 {
235 pci_write_config8(dev, 0xa9, 0x46);
236
237 RCBA32_AND_OR(0x232c, ~1, 0);
238
239 RCBA32_OR(0x1100, 0x0000c13f);
240
241 RCBA32_AND_OR(0x2320, ~0x60, 0x10);
242
243 RCBA32(0x3314) = 0x00012fff;
244
245 RCBA32_AND_OR(0x3318, ~0x000f0330, 0x0dcf0400);
246
247 RCBA32(0x3324) = 0x04000000;
248 RCBA32(0x3368) = 0x00041400;
249 RCBA32(0x3388) = 0x3f8ddbff;
250 RCBA32(0x33ac) = 0x00007001;
251 RCBA32(0x33b0) = 0x00181900;
252 RCBA32(0x33c0) = 0x00060A00;
253 RCBA32(0x33d0) = 0x06200840;
254 RCBA32(0x3a28) = 0x01010101;
255 RCBA32(0x3a2c) = 0x040c0404;
256 RCBA32(0x3a9c) = 0x9000000a;
257 RCBA32(0x2b1c) = 0x03808033;
258 RCBA32(0x2b34) = 0x80000009;
259 RCBA32(0x3348) = 0x022ddfff;
260 RCBA32(0x334c) = 0x00000001;
261 RCBA32(0x3358) = 0x0001c000;
262 RCBA32(0x3380) = 0x3f8ddbff;
263 RCBA32(0x3384) = 0x0001c7e1;
264 RCBA32(0x338c) = 0x0001c7e1;
265 RCBA32(0x3398) = 0x0001c000;
266 RCBA32(0x33a8) = 0x00181900;
267 RCBA32(0x33dc) = 0x00080000;
268 RCBA32(0x33e0) = 0x00000001;
269 RCBA32(0x3a20) = 0x0000040c;
270 RCBA32(0x3a24) = 0x01010101;
271 RCBA32(0x3a30) = 0x01010101;
272
273 pci_update_config32(dev, 0xac, ~0x00200000, 0);
274
275 RCBA32_OR(0x0410, 0x00000003);
276 RCBA32_OR(0x2618, 0x08000000);
277 RCBA32_OR(0x2300, 0x00000002);
278 RCBA32_OR(0x2600, 0x00000008);
279
280 RCBA32(0x33b4) = 0x00007001;
281 RCBA32(0x3350) = 0x022ddfff;
282 RCBA32(0x3354) = 0x00000001;
283
284 /* Power Optimizer */
285 RCBA32_OR(0x33d4, 0x08000000);
286 RCBA32_OR(0x33c8, 0x00000080);
287
288 RCBA32(0x2b10) = 0x0000883c;
289 RCBA32(0x2b14) = 0x1e0a4616;
290 RCBA32(0x2b24) = 0x40000005;
291 RCBA32(0x2b20) = 0x0005db01;
292 RCBA32(0x3a80) = 0x05145005;
293 RCBA32(0x3a84) = 0x00001005;
294
295 RCBA32_OR(0x33d4, 0x2fff2fb1);
296 RCBA32_OR(0x33c8, 0x00008000);
297 }
298
299 static void pch_enable_mphy(void)
300 {
301 u32 gpio71_native = gpio_is_native(71);
302 u32 data_and = 0xffffffff;
303 u32 data_or = (1 << 14) | (1 << 13) | (1 << 12);
304
305 if (gpio71_native) {
306 data_or |= (1 << 0);
307 if (pch_is_wpt()) {
308 data_and &= ~((1 << 7) | (1 << 6) | (1 << 3));
309 data_or |= (1 << 5) | (1 << 4);
310
311 if (pch_is_wpt_ulx()) {
312 /* Check if SATA and USB3 MPHY are enabled */
313 u32 strap19 = pch_read_soft_strap(19);
314 strap19 &= ((1 << 31) | (1 << 30));
315 strap19 >>= 30;
316 if (strap19 == 3) {
317 data_or |= (1 << 3);
318 printk(BIOS_DEBUG, "Enable ULX MPHY PG "
319 "control in single domain\n");
320 } else if (strap19 == 0) {
321 printk(BIOS_DEBUG, "Enable ULX MPHY PG "
322 "control in split domains\n");
323 } else {
324 printk(BIOS_DEBUG, "Invalid PCH Soft "
325 "Strap 19 configuration\n");
326 }
327 } else {
328 data_or |= (1 << 3);
329 }
330 }
331 }
332
333 pch_iobp_update(0xCF000000, data_and, data_or);
334 }
335
336 static void pch_init_deep_sx(struct device *dev)
337 {
338 const struct soc_intel_broadwell_pch_config *config = config_of(dev);
339
340 if (config->deep_sx_enable_ac) {
341 RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC);
342 RCBA32_OR(DEEP_S5_POL, DEEP_S5_EN_AC);
343 }
344
345 if (config->deep_sx_enable_dc) {
346 RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_DC);
347 RCBA32_OR(DEEP_S5_POL, DEEP_S5_EN_DC);
348 }
349
350 if (config->deep_sx_enable_ac || config->deep_sx_enable_dc)
351 RCBA32_OR(DEEP_SX_CONFIG,
352 DEEP_SX_WAKE_PIN_EN | DEEP_SX_GP27_PIN_EN);
353 }
354
355 /* Power Management init */
356 static void pch_pm_init(struct device *dev)
357 {
358 printk(BIOS_DEBUG, "PCH PM init\n");
359
360 pch_init_deep_sx(dev);
361
362 pch_enable_mphy();
363
364 pch_pm_init_magic(dev);
365
366 if (pch_is_wpt()) {
367 RCBA32_OR(0x33e0, (1 << 4) | (1 << 1));
368 RCBA32_OR(0x2b1c, (1 << 22) | (1 << 14) | (1 << 13));
369 RCBA32(0x33e4) = 0x16bf0002;
370 RCBA32_OR(0x33e4, 0x1);
371 }
372
373 pch_iobp_update(0xCA000000, ~0UL, 0x00000009);
374
375 /* Set RCBA 0x2b1c[29]=1 if DSP disabled */
376 if (RCBA32(FD) & PCH_DISABLE_ADSPD)
377 RCBA32_OR(0x2b1c, (1 << 29));
378
379 }
380
381 static void pch_cg_init(struct device *dev)
382 {
383 u32 reg32;
384 u16 reg16;
385 struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
386
387 /* DMI */
388 RCBA32_OR(0x2234, 0xf);
389
390 reg16 = pci_read_config16(dev, GEN_PMCON_1);
391 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
392 if (pch_is_wpt())
393 reg16 &= ~(1 << 11);
394 else
395 reg16 |= (1 << 11);
396 reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12);
397 reg16 |= (1 << 2); // PCI CLKRUN# Enable
398 pci_write_config16(dev, GEN_PMCON_1, reg16);
399
400 /*
401 * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1
402 * RCBA + 0x2614[23:16] = 0x20
403 * RCBA + 0x2614[30:28] = 0x0
404 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b)
405 */
406 RCBA32_AND_OR(0x2614, ~0x64ff0000, 0x0a206500);
407
408 /* Check for 0:2.0@0x08 >= 0x0b */
409 if (pch_is_wpt() || pci_read_config8(igd_dev, 0x8) >= 0x0b)
410 RCBA32_OR(0x2614, (1 << 26));
411
412 RCBA32_OR(0x900, 0x0000031f);
413
414 reg32 = RCBA32(CG);
415 if (RCBA32(0x3454) & (1 << 4))
416 reg32 &= ~(1 << 29); // LPC Dynamic
417 else
418 reg32 |= (1 << 29); // LPC Dynamic
419 reg32 |= (1 << 31); // LP LPC
420 reg32 |= (1 << 30); // LP BLA
421 if (RCBA32(0x3454) & (1 << 4))
422 reg32 &= ~(1 << 29);
423 else
424 reg32 |= (1 << 29);
425 reg32 |= (1 << 28); // GPIO Dynamic
426 reg32 |= (1 << 27); // HPET Dynamic
427 reg32 |= (1 << 26); // Generic Platform Event Clock
428 if (RCBA32(BUC) & PCH_DISABLE_GBE)
429 reg32 |= (1 << 23); // GbE Static
430 if (RCBA32(FD) & PCH_DISABLE_HD_AUDIO)
431 reg32 |= (1 << 21); // HDA Static
432 reg32 |= (1 << 22); // HDA Dynamic
433 RCBA32(CG) = reg32;
434
435 /* PCH-LP LPC */
436 if (pch_is_wpt())
437 RCBA32_AND_OR(0x3434, ~0x1f, 0x17);
438 else
439 RCBA32_OR(0x3434, 0x7);
440
441 /* SPI */
442 RCBA32_OR(0x38c0, 0x3c07);
443
444 pch_iobp_update(0xCE00C000, ~1UL, 0x00000000);
445 }
446
447 static void pch_set_acpi_mode(void)
448 {
449 if (!acpi_is_wakeup_s3()) {
450 apm_control(APM_CNT_ACPI_DISABLE);
451 }
452 }
453
454 static void lpc_init(struct device *dev)
455 {
456 /* Legacy initialization */
457 isa_dma_init();
458 sb_rtc_init();
459 pch_misc_init(dev);
460
461 /* Interrupt configuration */
462 pch_enable_ioapic(dev);
463 pch_pirq_init(dev);
464 setup_i8259();
465 i8259_configure_irq_trigger(9, 1);
466 enable_hpet(dev);
467
468 /* Initialize power management */
469 pch_power_options(dev);
470 pch_pm_init(dev);
471 pch_cg_init(dev);
472
473 pch_set_acpi_mode();
474 }
475
476 static void pch_lpc_add_mmio_resources(struct device *dev)
477 {
478 u32 reg;
479 struct resource *res;
480 const u32 default_decode_base = IO_APIC_ADDR;
481
482 /*
483 * Just report all resources from IO-APIC base to 4GiB. Don't mark
484 * them reserved as that may upset the OS if this range is marked
485 * as reserved in the e820.
486 */
487 res = new_resource(dev, OIC);
488 res->base = default_decode_base;
489 res->size = 0 - default_decode_base;
490 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
491
492 /* RCBA */
493 if (default_decode_base > RCBA_BASE_ADDRESS) {
494 res = new_resource(dev, RCBA);
495 res->base = RCBA_BASE_ADDRESS;
496 res->size = 16 * 1024;
497 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
498 IORESOURCE_FIXED | IORESOURCE_RESERVE;
499 }
500
501 /* Check LPC Memory Decode register. */
502 reg = pci_read_config32(dev, LGMR);
503 if (reg & 1) {
504 reg &= ~0xffff;
505 if (reg < default_decode_base) {
506 res = new_resource(dev, LGMR);
507 res->base = reg;
508 res->size = 16 * 1024;
509 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
510 IORESOURCE_FIXED | IORESOURCE_RESERVE;
511 }
512 }
513 }
514
515 /* Default IO range claimed by the LPC device. The upper bound is exclusive. */
516 #define LPC_DEFAULT_IO_RANGE_LOWER 0
517 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
518
519 static inline int pch_io_range_in_default(int base, int size)
520 {
521 /* Does it start above the range? */
522 if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
523 return 0;
524
525 /* Is it entirely contained? */
526 if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
527 (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
528 return 1;
529
530 /* This will return not in range for partial overlaps. */
531 return 0;
532 }
533
534 /*
535 * Note: this function assumes there is no overlap with the default LPC device's
536 * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
537 */
538 static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size,
539 int index)
540 {
541 struct resource *res;
542
543 if (pch_io_range_in_default(base, size))
544 return;
545
546 res = new_resource(dev, index);
547 res->base = base;
548 res->size = size;
549 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
550 }
551
552 static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
553 int index)
554 {
555 /*
556 * Check if the register is enabled. If so and the base exceeds the
557 * device's default claim range add the resource.
558 */
559 if (reg_value & 1) {
560 u16 base = reg_value & 0xfffc;
561 u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1;
562 pch_lpc_add_io_resource(dev, base, size, index);
563 }
564 }
565
566 static void pch_lpc_add_io_resources(struct device *dev)
567 {
568 struct resource *res;
569 const struct soc_intel_broadwell_pch_config *config = config_of(dev);
570
571 /* Add the default claimed IO range for the LPC device. */
572 res = new_resource(dev, 0);
573 res->base = LPC_DEFAULT_IO_RANGE_LOWER;
574 res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
575 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
576
577 /* GPIOBASE */
578 pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS,
579 GPIO_BASE_SIZE, GPIO_BASE);
580
581 /* PMBASE */
582 pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE);
583
584 /* LPC Generic IO Decode range. */
585 pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
586 pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
587 pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);
588 pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
589 }
590
591 static void pch_lpc_read_resources(struct device *dev)
592 {
593 /* Get the normal PCI resources of this device. */
594 pci_dev_read_resources(dev);
595
596 /* Add non-standard MMIO resources. */
597 pch_lpc_add_mmio_resources(dev);
598
599 /* Add IO resources. */
600 pch_lpc_add_io_resources(dev);
601 }
602
603 void soc_fill_gnvs(struct global_nvs *gnvs)
604 {
605 /* Set unknown wake source */
606 gnvs->pm1i = -1;
607
608 /* CPU core count */
609 gnvs->pcnt = dev_count_cpu();
610 }
611
612 static void southcluster_inject_dsdt(const struct device *device)
613 {
614 struct global_nvs *gnvs = acpi_get_gnvs();
615 if (!gnvs)
616 return;
617
618 soc_fill_gnvs(gnvs);
619 acpi_create_gnvs(gnvs);
620 acpi_inject_nvsa();
621 }
622
623 static unsigned long broadwell_write_acpi_tables(const struct device *device,
624 unsigned long current,
625 struct acpi_rsdp *rsdp)
626 {
627 if (CONFIG(INTEL_PCH_UART_CONSOLE))
628 current = acpi_write_dbg2_pci_uart(rsdp, current,
629 (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1) ?
630 PCH_DEV_UART1 : PCH_DEV_UART0,
631 ACPI_ACCESS_SIZE_BYTE_ACCESS);
632 return acpi_write_hpet(device, current, rsdp);
633 }
634
635 static struct device_operations device_ops = {
636 .read_resources = &pch_lpc_read_resources,
637 .set_resources = &pci_dev_set_resources,
638 .enable_resources = &pci_dev_enable_resources,
639 .acpi_inject_dsdt = southcluster_inject_dsdt,
640 .write_acpi_tables = broadwell_write_acpi_tables,
641 .init = &lpc_init,
642 .scan_bus = &scan_static_bus,
643 .ops_pci = &pci_dev_ops_pci,
644 };
645
646 static const unsigned short pci_device_ids[] = {
647 PCH_LPT_LP_SAMPLE,
648 PCH_LPT_LP_PREMIUM,
649 PCH_LPT_LP_MAINSTREAM,
650 PCH_LPT_LP_VALUE,
651 PCH_WPT_HSW_U_SAMPLE,
652 PCH_WPT_BDW_U_SAMPLE,
653 PCH_WPT_BDW_U_PREMIUM,
654 PCH_WPT_BDW_U_BASE,
655 PCH_WPT_BDW_Y_SAMPLE,
656 PCH_WPT_BDW_Y_PREMIUM,
657 PCH_WPT_BDW_Y_BASE,
658 PCH_WPT_BDW_H,
659 0
660 };
661
662 static const struct pci_driver pch_lpc __pci_driver = {
663 .ops = &device_ops,
664 .vendor = PCI_VENDOR_ID_INTEL,
665 .devices = pci_device_ids,
666 };
ast, secure and flexible OpenSource firmware