src/southbridge/intel/bd82x6x/watchdog.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2011 Google Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <console/console.h>
  19 #include <arch/io.h>
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <watchdog.h>
  23
  24   //
  25   //  Disable PCH Watchdog timer at SB_RCBA+0x3410
  26   //
  27   //  Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20;
  28   //
  29 void watchdog_off(void)
  30 {
  31         struct device *dev;
  32         unsigned long value, base;
  33
  34         /* Turn off the ICH7 watchdog. */
  35         dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
  36
  37         /* Enable I/O space. */
  38         value = pci_read_config16(dev, 0x04);
  39         value |= (1 << 10);
  40         pci_write_config16(dev, 0x04, value);
  41
  42         /* Get TCO base. */
  43         base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
  44
  45         /* Disable the watchdog timer. */
  46         value = inw(base + 0x08);
  47         value |= 1 << 11;
  48         outw(value, base + 0x08);
  49
  50         /* Clear TCO timeout status. */
  51         outw(0x0008, base + 0x04);
  52         outw(0x0002, base + 0x06);
  53
  54         printk(BIOS_DEBUG, "PCH watchdog disabled\n");
  55 }