2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <southbridge/intel/common/rcba.h>
23 #include <device/pci_ehci.h>
26 static void usb_ehci_init(struct device
*dev
)
30 /* Disable Wake on Disconnect in RMH */
31 reg32
= RCBA32(0x35b0);
33 RCBA32(0x35b0) = reg32
;
35 printk(BIOS_DEBUG
, "EHCI: Setting up controller.. ");
37 /* For others, done in MRC. */
38 #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
39 pci_write_config32(dev
, 0x84, 0x930c8811);
40 pci_write_config32(dev
, 0x88, 0x24000d30);
41 pci_write_config32(dev
, 0xf4, 0x80408588);
42 pci_write_config32(dev
, 0xf4, 0x80808588);
43 pci_write_config32(dev
, 0xf4, 0x00808588);
44 pci_write_config32(dev
, 0xfc, 0x205b1708);
47 reg32
= pci_read_config32(dev
, PCI_COMMAND
);
48 reg32
|= PCI_COMMAND_MASTER
;
49 //reg32 |= PCI_COMMAND_SERR;
50 pci_write_config32(dev
, PCI_COMMAND
, reg32
);
52 /* For others, done in MRC. */
53 #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
57 access_cntl
= pci_read_config8(dev
, 0x80);
59 /* Enable writes to protected registers. */
60 pci_write_config8(dev
, 0x80, access_cntl
| 1);
62 res
= find_resource(dev
, PCI_BASE_ADDRESS_0
);
64 /* Number of ports and companion controllers. */
65 reg32
= read32((void *)(uintptr_t)(res
->base
+ 4));
66 write32((void *)(uintptr_t)(res
->base
+ 4),
67 (reg32
& 0xfff00000) | 3);
70 /* Restore protection. */
71 pci_write_config8(dev
, 0x80, access_cntl
);
74 printk(BIOS_DEBUG
, "done.\n");
77 static void usb_ehci_set_subsystem(struct device
*dev
, unsigned vendor
,
82 access_cntl
= pci_read_config8(dev
, 0x80);
84 /* Enable writes to protected registers. */
85 pci_write_config8(dev
, 0x80, access_cntl
| 1);
87 if (!vendor
|| !device
) {
88 pci_write_config32(dev
, PCI_SUBSYSTEM_VENDOR_ID
,
89 pci_read_config32(dev
, PCI_VENDOR_ID
));
91 pci_write_config32(dev
, PCI_SUBSYSTEM_VENDOR_ID
,
92 ((device
& 0xffff) << 16) | (vendor
& 0xffff));
95 /* Restore protection. */
96 pci_write_config8(dev
, 0x80, access_cntl
);
99 static const char *usb_ehci_acpi_name(const struct device
*dev
)
101 switch (dev
->path
.pci
.devfn
) {
102 case PCI_DEVFN(0x1a, 0):
104 case PCI_DEVFN(0x1d, 0):
110 static struct pci_operations lops_pci
= {
111 .set_subsystem
= &usb_ehci_set_subsystem
,
114 static struct device_operations usb_ehci_ops
= {
115 .read_resources
= pci_ehci_read_resources
,
116 .set_resources
= pci_dev_set_resources
,
117 .enable_resources
= pci_dev_enable_resources
,
118 .init
= usb_ehci_init
,
120 .ops_pci
= &lops_pci
,
121 .acpi_name
= usb_ehci_acpi_name
,
124 static const unsigned short pci_device_ids
[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d,
127 static const struct pci_driver pch_usb_ehci __pci_driver
= {
128 .ops
= &usb_ehci_ops
,
129 .vendor
= PCI_VENDOR_ID_INTEL
,
130 .devices
= pci_device_ids
,