src/southbridge/intel/bd82x6x/sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include "pch.h"
  23 #include <pc80/mc146818rtc.h>
  24 #include <acpi/sata.h>
  25
  26 typedef struct southbridge_intel_bd82x6x_config config_t;
  27
  28 static inline u32 sir_read(struct device *dev, int idx)
  29 {
  30         pci_write_config32(dev, SATA_SIRI, idx);
  31         return pci_read_config32(dev, SATA_SIRD);
  32 }
  33
  34 static inline void sir_write(struct device *dev, int idx, u32 value)
  35 {
  36         pci_write_config32(dev, SATA_SIRI, idx);
  37         pci_write_config32(dev, SATA_SIRD, value);
  38 }
  39
  40 static void sata_init(struct device *dev)
  41 {
  42         u32 reg32;
  43         u16 reg16;
  44         /* Get the chip configuration */
  45         config_t *config = dev->chip_info;
  46         u8 sata_mode;
  47
  48         printk(BIOS_DEBUG, "SATA: Initializing...\n");
  49
  50         if (config == NULL) {
  51                 printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
  52                 return;
  53         }
  54
  55         if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
  56                 /* Default to AHCI */
  57                 sata_mode = 0;
  58
  59         /* SATA configuration */
  60
  61         /* Enable BARs */
  62         pci_write_config16(dev, PCI_COMMAND, 0x0007);
  63
  64         /* AHCI */
  65         if (sata_mode == 0) {
  66                 u8 *abar;
  67
  68                 printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
  69
  70                 /* Set Interrupt Line */
  71                 /* Interrupt Pin is set by D31IP.PIP */
  72                 pci_write_config8(dev, INTR_LN, 0x0a);
  73
  74                 /* Set timings */
  75                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
  76                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
  77                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
  78                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
  79                                 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
  80
  81                 /* Sync DMA */
  82                 pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
  83                 pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
  84
  85                 /* Set IDE I/O Configuration */
  86                 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
  87                 pci_write_config32(dev, IDE_CONFIG, reg32);
  88
  89                 /* for AHCI, Port Enable is managed in memory mapped space */
  90                 reg16 = pci_read_config16(dev, 0x92);
  91                 reg16 &= ~0x3f; /* 6 ports SKU + ORM */
  92                 reg16 |= 0x8000 | config->sata_port_map;
  93                 pci_write_config16(dev, 0x92, reg16);
  94
  95                 /* SATA Initialization register */
  96                 pci_write_config32(dev, 0x94,
  97                            ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
  98
  99                 /* Initialize AHCI memory-mapped space */
 100                 abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
 101                 printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 102                 /* CAP (HBA Capabilities) : enable power management */
 103                 reg32 = read32(abar + 0x00);
 104                 reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
 105                 reg32 &= ~0x00020060; // clear SXS+EMS+PMS
 106                 /* Set ISS, if available */
 107                 if (config->sata_interface_speed_support)
 108                 {
 109                         reg32 &= ~0x00f00000;
 110                         reg32 |= (config->sata_interface_speed_support & 0x03)
 111                           << 20;
 112                 }
 113                 write32(abar + 0x00, reg32);
 114                 /* PI (Ports implemented) */
 115                 write32(abar + 0x0c, config->sata_port_map);
 116                 (void) read32(abar + 0x0c); /* Read back 1 */
 117                 (void) read32(abar + 0x0c); /* Read back 2 */
 118                 /* CAP2 (HBA Capabilities Extended)*/
 119                 reg32 = read32(abar + 0x24);
 120                 reg32 &= ~0x00000002;
 121                 write32(abar + 0x24, reg32);
 122                 /* VSP (Vendor Specific Register */
 123                 reg32 = read32(abar + 0xa0);
 124                 reg32 &= ~0x00000005;
 125                 write32(abar + 0xa0, reg32);
 126         } else {
 127                 /* IDE */
 128                 printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
 129
 130                 /* No AHCI: clear AHCI base */
 131                 pci_write_config32(dev, 0x24, 0x00000000);
 132
 133                 /* And without AHCI BAR no memory decoding */
 134                 reg16 = pci_read_config16(dev, PCI_COMMAND);
 135                 reg16 &= ~PCI_COMMAND_MEMORY;
 136                 pci_write_config16(dev, PCI_COMMAND, reg16);
 137
 138                 /* Native mode capable on both primary and secondary (0xa)
 139                  * or'ed with enabled (0x50) = 0xf
 140                  */
 141                 pci_write_config8(dev, 0x09, 0x8f);
 142
 143                 /* Set Interrupt Line */
 144                 /* Interrupt Pin is set by D31IP.PIP */
 145                 pci_write_config8(dev, INTR_LN, 0xff);
 146
 147                 /* Set timings */
 148                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
 149                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
 150                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
 151                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
 152                                 IDE_SITRE | IDE_ISP_3_CLOCKS |
 153                                 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
 154
 155                 /* Sync DMA */
 156                 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
 157                 pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
 158
 159                 /* Set IDE I/O Configuration */
 160                 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
 161                 pci_write_config32(dev, IDE_CONFIG, reg32);
 162
 163                 /* Port enable */
 164                 reg16 = pci_read_config16(dev, 0x92);
 165                 reg16 &= ~0x3f;
 166                 reg16 |= config->sata_port_map;
 167                 pci_write_config16(dev, 0x92, reg16);
 168
 169                 /* SATA Initialization register */
 170                 pci_write_config32(dev, 0x94,
 171                            ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
 172         }
 173
 174         /* Set Gen3 Transmitter settings if needed */
 175         if (config->sata_port0_gen3_tx)
 176                 pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
 177                                 config->sata_port0_gen3_tx);
 178
 179         if (config->sata_port1_gen3_tx)
 180                 pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
 181                                 config->sata_port1_gen3_tx);
 182
 183         /* Additional Programming Requirements */
 184         sir_write(dev, 0x04, 0x00001600);
 185         sir_write(dev, 0x28, 0xa0000033);
 186         reg32 = sir_read(dev, 0x54);
 187         reg32 &= 0xff000000;
 188         reg32 |= 0x5555aa;
 189         sir_write(dev, 0x54, reg32);
 190         sir_write(dev, 0x64, 0xcccc8484);
 191         reg32 = sir_read(dev, 0x68);
 192         reg32 &= 0xffff0000;
 193         reg32 |= 0xcccc;
 194         sir_write(dev, 0x68, reg32);
 195         reg32 = sir_read(dev, 0x78);
 196         reg32 &= 0x0000ffff;
 197         reg32 |= 0x88880000;
 198         sir_write(dev, 0x78, reg32);
 199         sir_write(dev, 0x84, 0x001c7000);
 200         sir_write(dev, 0x88, 0x88338822);
 201         sir_write(dev, 0xa0, 0x001c7000);
 202         // a4
 203         sir_write(dev, 0xc4, 0x0c0c0c0c);
 204         sir_write(dev, 0xc8, 0x0c0c0c0c);
 205         sir_write(dev, 0xd4, 0x10000000);
 206
 207         pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
 208         pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
 209 }
 210
 211 static void sata_enable(struct device *dev)
 212 {
 213         /* Get the chip configuration */
 214         config_t *config = dev->chip_info;
 215         u16 map = 0;
 216         u8 sata_mode;
 217
 218         if (!config)
 219                 return;
 220
 221         if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
 222                 sata_mode = 0;
 223
 224         /*
 225          * Set SATA controller mode early so the resource allocator can
 226          * properly assign IO/Memory resources for the controller.
 227          */
 228         if (sata_mode == 0)
 229                 map = 0x0060;
 230
 231         map |= (config->sata_port_map ^ 0x3f) << 8;
 232
 233         pci_write_config16(dev, 0x90, map);
 234 }
 235
 236 static void sata_set_subsystem(struct device *dev, unsigned vendor,
 237                                unsigned device)
 238 {
 239         if (!vendor || !device) {
 240                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 241                                 pci_read_config32(dev, PCI_VENDOR_ID));
 242         } else {
 243                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 244                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 245         }
 246 }
 247
 248 static const char *sata_acpi_name(const struct device *dev)
 249 {
 250         return "SATA";
 251 }
 252
 253 static void sata_fill_ssdt(struct device *dev)
 254 {
 255         config_t *config = dev->chip_info;
 256         generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
 257 }
 258
 259 static struct pci_operations sata_pci_ops = {
 260         .set_subsystem    = sata_set_subsystem,
 261 };
 262
 263 static struct device_operations sata_ops = {
 264         .read_resources         = pci_dev_read_resources,
 265         .set_resources          = pci_dev_set_resources,
 266         .enable_resources       = pci_dev_enable_resources,
 267         .acpi_fill_ssdt_generator
 268                                 = sata_fill_ssdt,
 269         .init                   = sata_init,
 270         .enable                 = sata_enable,
 271         .scan_bus               = 0,
 272         .ops_pci                = &sata_pci_ops,
 273         .acpi_name              = sata_acpi_name,
 274 };
 275
 276 static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03,
 277                                                  0x1e00, 0x1e01, 0x1e02, 0x1e03,
 278                                                  0 };
 279
 280 static const struct pci_driver pch_sata __pci_driver = {
 281         .ops     = &sata_ops,
 282         .vendor  = PCI_VENDOR_ID_INTEL,
 283         .devices = pci_device_ids,
 284 };