src/northbridge/amd/amdfam10/misc_control.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 by Eric Biederman
   5  * Copyright (C) Stefan Reinauer
   6  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   7  * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
   8  * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; version 2 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 /* Turn off machine check triggers when reading
  21  * pci space where there are no devices.
  22  * This is necessary when scaning the bus for
  23  * devices which is done by the kernel
  24  */
  25
  26 #include <console/console.h>
  27 #include <device/device.h>
  28 #include <device/pci.h>
  29 #include <device/pci_ids.h>
  30 #include <device/pci_ops.h>
  31 #include <pc80/mc146818rtc.h>
  32 #include <lib.h>
  33 #include <cbmem.h>
  34 #include <cpu/amd/model_10xxx_rev.h>
  35
  36 #include "amdfam10.h"
  37
  38 /**
  39  * @brief Read resources for AGP aperture
  40  *
  41  * @param dev
  42  *
  43  * There is only one AGP aperture resource needed. The resource is added to
  44  * the northbridge of BSP.
  45  *
  46  * The same trick can be used to augment legacy VGA resources which can
  47  * be detect by generic pci reousrce allocator for VGA devices.
  48  * BAD: it is more tricky than I think, the resource allocation code is
  49  * implemented in a way to NOT DOING legacy VGA resource allocation on
  50  * purpose :-(.
  51  */
  52 static void mcf3_read_resources(device_t dev)
  53 {
  54         struct resource *resource;
  55         unsigned char gart;
  56         /* Read the generic PCI resources */
  57         pci_dev_read_resources(dev);
  58
  59         /* If we are not the first processor don't allocate the gart apeture */
  60         if (dev->path.pci.devfn != PCI_DEVFN(CONFIG_CDB, 3)) {
  61                 return;
  62         }
  63
  64         gart = 1;
  65         get_option(&gart, "gart");
  66
  67         if (gart) {
  68                 /* Add a Gart apeture resource */
  69                 resource = new_resource(dev, 0x94);
  70                 resource->size = CONFIG_AGP_APERTURE_SIZE;
  71                 resource->align = log2(resource->size);
  72                 resource->gran  = log2(resource->size);
  73                 resource->limit = 0xffffffff; /* 4G */
  74                 resource->flags = IORESOURCE_MEM;
  75         }
  76 }
  77
  78 static void set_agp_aperture(device_t dev, uint32_t pci_id)
  79 {
  80         uint32_t dword;
  81         struct resource *resource;
  82
  83         resource = probe_resource(dev, 0x94);
  84         if (resource) {
  85                 device_t pdev;
  86                 u32 gart_base, gart_acr;
  87
  88                 /* Remember this resource has been stored */
  89                 resource->flags |= IORESOURCE_STORED;
  90
  91                 /* Find the size of the GART aperture */
  92                 gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
  93
  94                 /* Get the base address */
  95                 gart_base = ((resource->base) >> 25) & 0x00007fff;
  96
  97                 /* Update the other northbriges */
  98                 pdev = 0;
  99                 while ((pdev = dev_find_device(PCI_VENDOR_ID_AMD, pci_id, pdev))) {
 100                         /* Store the GART size but don't enable it */
 101                         pci_write_config32(pdev, 0x90, gart_acr);
 102
 103                         /* Store the GART base address */
 104                         pci_write_config32(pdev, 0x94, gart_base);
 105
 106                         /* Don't set the GART Table base address */
 107                         pci_write_config32(pdev, 0x98, 0);
 108
 109                         /* Report the resource has been stored... */
 110                         report_resource_stored(pdev, resource, " <gart>");
 111
 112                         /* Errata 540 workaround */
 113                         dword = pci_read_config32(pdev, 0x90);
 114                         dword |= 0x1 << 6;                      /* DisGartTblWlkPrb = 0x1 */
 115                         pci_write_config32(pdev, 0x90, dword);
 116                 }
 117         }
 118 }
 119
 120 static void mcf3_set_resources_fam10h(device_t dev)
 121 {
 122         /* Set the gart aperture */
 123         set_agp_aperture(dev, 0x1203);
 124
 125         /* Set the generic PCI resources */
 126         pci_dev_set_resources(dev);
 127 }
 128
 129 static void mcf3_set_resources_fam15h_model10(device_t dev)
 130 {
 131         /* Set the gart aperture */
 132         set_agp_aperture(dev, 0x1403);
 133
 134         /* Set the generic PCI resources */
 135         pci_dev_set_resources(dev);
 136 }
 137
 138 static void mcf3_set_resources_fam15h(device_t dev)
 139 {
 140         /* Set the gart aperture */
 141         set_agp_aperture(dev, 0x1603);
 142
 143         /* Set the generic PCI resources */
 144         pci_dev_set_resources(dev);
 145 }
 146
 147 static void misc_control_init(struct device *dev)
 148 {
 149         uint32_t dword;
 150         uint8_t nvram;
 151         uint8_t boost_limit;
 152         uint8_t current_boost;
 153
 154         printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 155
 156 #if IS_ENABLED(CONFIG_DIMM_DDR3) && !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA)
 157         uint8_t node;
 158         uint8_t slot;
 159         uint8_t dimm_present;
 160
 161         /* Restore DRAM MCA registers */
 162         struct amdmct_memory_info *mem_info;
 163         mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO);
 164         if (mem_info) {
 165                 node = PCI_SLOT(dev->path.pci.devfn) - 0x18;
 166
 167                 /* Check node for installed DIMMs */
 168                 dimm_present = 0;
 169
 170                 /* Check all slots for installed DIMMs */
 171                 for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) {
 172                         if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) {
 173                                 dimm_present = 1;
 174                                 break;
 175                         }
 176                 }
 177
 178                 if (dimm_present) {
 179                         uint32_t mc4_status_high = pci_read_config32(dev, 0x4c);
 180                         uint32_t mc4_status_low = pci_read_config32(dev, 0x48);
 181                         if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) {
 182                                 printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n"
 183                                         "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low);
 184                         }
 185
 186                         /* Clear MC4 error status */
 187                         pci_write_config32(dev, 0x48, 0x0);
 188                         pci_write_config32(dev, 0x4c, 0x0);
 189                 }
 190         }
 191 #endif
 192
 193         /* Disable Machine checks from Invalid Locations.
 194          * This is needed for PC backwards compatibility.
 195          */
 196         dword = pci_read_config32(dev, 0x44);
 197         dword |= (1<<6) | (1<<25);
 198         pci_write_config32(dev, 0x44, dword);
 199
 200         boost_limit = 0xf;
 201         if (get_option(&nvram, "maximum_p_state_limit") == CB_SUCCESS)
 202                 boost_limit = nvram & 0xf;
 203
 204         /* Set P-state maximum value */
 205         dword = pci_read_config32(dev, 0xdc);
 206         current_boost = (dword >> 8) & 0x7;
 207         if (boost_limit > current_boost)
 208                 boost_limit = current_boost;
 209         dword &= ~(0x7 << 8);
 210         dword |= (boost_limit & 0x7) << 8;
 211         pci_write_config32(dev, 0xdc, dword);
 212
 213         printk(BIOS_DEBUG, "done.\n");
 214 }
 215
 216
 217 static struct device_operations mcf3_ops_fam10h  = {
 218         .read_resources   = mcf3_read_resources,
 219         .set_resources    = mcf3_set_resources_fam10h,
 220         .enable_resources = pci_dev_enable_resources,
 221         .init             = misc_control_init,
 222         .scan_bus         = 0,
 223         .ops_pci          = 0,
 224 };
 225
 226 static struct device_operations mcf3_ops_fam15h_model10  = {
 227         .read_resources   = mcf3_read_resources,
 228         .set_resources    = mcf3_set_resources_fam15h_model10,
 229         .enable_resources = pci_dev_enable_resources,
 230         .init             = misc_control_init,
 231         .scan_bus         = 0,
 232         .ops_pci          = 0,
 233 };
 234
 235 static struct device_operations mcf3_ops_fam15h  = {
 236         .read_resources   = mcf3_read_resources,
 237         .set_resources    = mcf3_set_resources_fam15h,
 238         .enable_resources = pci_dev_enable_resources,
 239         .init             = misc_control_init,
 240         .scan_bus         = 0,
 241         .ops_pci          = 0,
 242 };
 243
 244 static const struct pci_driver mcf3_driver __pci_driver = {
 245         .ops    = &mcf3_ops_fam10h,
 246         .vendor = PCI_VENDOR_ID_AMD,
 247         .device = 0x1203,
 248 };
 249
 250 static const struct pci_driver mcf3_driver_fam15_model10 __pci_driver = {
 251         .ops    = &mcf3_ops_fam15h_model10,
 252         .vendor = PCI_VENDOR_ID_AMD,
 253         .device = 0x1403,
 254 };
 255
 256 static const struct pci_driver mcf3_driver_fam15 __pci_driver = {
 257         .ops    = &mcf3_ops_fam15h,
 258         .vendor = PCI_VENDOR_ID_AMD,
 259         .device = 0x1603,
 260 };