src/mainboard/nvidia/l1_2pvv/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20  */
  21
  22 #include <stdint.h>
  23 #include <string.h>
  24 #include <device/pci_def.h>
  25 #include <device/pci_ids.h>
  26 #include <arch/io.h>
  27 #include <device/pnp_def.h>
  28 #include <cpu/x86/lapic.h>
  29 #include <pc80/mc146818rtc.h>
  30 #include <console/console.h>
  31 #include <lib.h>
  32 #include <spd.h>
  33 #include <cpu/amd/model_fxx_rev.h>
  34 #include "southbridge/nvidia/mcp55/early_smbus.c"
  35 #include <northbridge/amd/amdk8/raminit.h>
  36 #include "lib/delay.c"
  37 #include <cpu/x86/lapic.h>
  38 #include "northbridge/amd/amdk8/reset_test.c"
  39 #include <superio/winbond/common/winbond.h>
  40 #include <superio/winbond/w83627ehg/w83627ehg.h>
  41 #include <cpu/x86/bist.h>
  42 #include "northbridge/amd/amdk8/debug.c"
  43 #include "northbridge/amd/amdk8/setup_resource_map.c"
  44 #include "southbridge/nvidia/mcp55/early_ctrl.c"
  45
  46 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  47
  48 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  49 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  50
  51 static inline int spd_read_byte(unsigned device, unsigned address)
  52 {
  53         return smbus_read_byte(device, address);
  54 }
  55
  56 #include <northbridge/amd/amdk8/f.h>
  57 #include "northbridge/amd/amdk8/incoherent_ht.c"
  58 #include "northbridge/amd/amdk8/coherent_ht.c"
  59 #include "northbridge/amd/amdk8/raminit_f.c"
  60 #include "lib/generic_sdram.c"
  61 #include "resourcemap.c"
  62 #include "cpu/amd/dualcore/dualcore.c"
  63
  64 #define MCP55_MB_SETUP \
  65         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
  66         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
  67         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
  68         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
  69         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
  70         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
  71
  72 #include <southbridge/nvidia/mcp55/early_setup_ss.h>
  73 #include "southbridge/nvidia/mcp55/early_setup_car.c"
  74 #include "cpu/amd/model_fxx/init_cpus.c"
  75 #include "cpu/amd/model_fxx/fidvid.c"
  76 #include "northbridge/amd/amdk8/early_ht.c"
  77
  78 static void sio_setup(void)
  79 {
  80         uint32_t dword;
  81         uint8_t byte;
  82
  83         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
  84         byte |= 0x20;
  85         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
  86
  87         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
  88         dword |= (1<<0);
  89         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
  90
  91         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
  92         dword |= (1<<16);
  93         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
  94 }
  95
  96 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  97 {
  98         static const uint16_t spd_addr [] = {
  99                 // Node 0
 100                 DIMM0, DIMM2, 0, 0,
 101                 DIMM1, DIMM3, 0, 0,
 102                 // Node 1
 103                 DIMM4, DIMM6, 0, 0,
 104                 DIMM5, DIMM7, 0, 0,
 105         };
 106
 107         struct sys_info *sysinfo = &sysinfo_car;
 108         int needs_reset = 0;
 109         unsigned bsp_apicid = 0;
 110
 111         if (!cpu_init_detectedx && boot_cpu()) {
 112                 /* Nothing special needs to be done to find bus 0 */
 113                 /* Allow the HT devices to be found */
 114                 enumerate_ht_chain();
 115                 sio_setup();
 116         }
 117
 118         if (bist == 0)
 119                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 120
 121         pnp_enter_ext_func_mode(SERIAL_DEV);
 122         pnp_write_config(SERIAL_DEV, 0x24, 0);
 123         pnp_exit_ext_func_mode(SERIAL_DEV);
 124
 125         setup_mb_resource_map();
 126
 127         winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 128         console_init();
 129
 130         /* Halt if there was a built in self test failure */
 131         report_bist_failure(bist);
 132         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 133
 134         printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 135
 136         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 137         setup_coherent_ht_domain(); // routing table and start other core0
 138
 139         wait_all_core0_started();
 140 #if CONFIG_LOGICAL_CPUS
 141         // It is said that we should start core1 after all core0 launched
 142         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 143          * So here need to make sure last core0 is started, esp for two way system,
 144          * (there may be apic id conflicts in that case)
 145          */
 146         start_other_cores();
 147         wait_all_other_cores_started(bsp_apicid);
 148 #endif
 149
 150         /* it will set up chains and store link pair for optimization later */
 151         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 152
 153 #if CONFIG_SET_FIDVID
 154         {
 155                 msr_t msr;
 156                 msr=rdmsr(0xc0010042);
 157                 printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 158         }
 159         enable_fid_change();
 160         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 161         init_fidvid_bsp(bsp_apicid);
 162         // show final fid and vid
 163         {
 164                 msr_t msr;
 165                 msr=rdmsr(0xc0010042);
 166                 printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 167         }
 168 #endif
 169
 170         init_timer(); /* Need to use TMICT to synchronize FID/VID. */
 171
 172         needs_reset |= optimize_link_coherent_ht();
 173         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 174         needs_reset |= mcp55_early_setup_x();
 175
 176         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 177         if (needs_reset) {
 178                 printk(BIOS_INFO, "ht reset -\n");
 179                 soft_reset();
 180         }
 181         allow_all_aps_stop(bsp_apicid);
 182
 183         //It's the time to set ctrl in sysinfo now;
 184         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 185
 186         enable_smbus();
 187
 188         /* all ap stopped? */
 189
 190         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 191
 192         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 193 }