src/mainboard/iwill/dk8_htx/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <device/pci_ids.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <pc80/mc146818rtc.h>
   8 #include <console/console.h>
   9 #include <cpu/amd/model_fxx_rev.h>
  10 #include "southbridge/amd/amd8111/early_smbus.c"
  11 #include <northbridge/amd/amdk8/raminit.h>
  12 #include "northbridge/amd/amdk8/reset_test.c"
  13 #include <cpu/x86/bist.h>
  14 #include <delay.h>
  15 #include "northbridge/amd/amdk8/debug.c"
  16 #include <superio/winbond/common/winbond.h>
  17 #include <superio/winbond/w83627hf/w83627hf.h>
  18 #include "northbridge/amd/amdk8/setup_resource_map.c"
  19 #include "southbridge/amd/amd8111/early_ctrl.c"
  20
  21 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  22
  23 /*
  24  * GPIO28 of 8111 will control H0_MEMRESET_L
  25  * GPIO29 of 8111 will control H1_MEMRESET_L
  26  */
  27 static void memreset_setup(void)
  28 {
  29         if (is_cpu_pre_c0()) {
  30                 /* Set the memreset low. */
  31                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  32                 /* Ensure the BIOS has control of the memory lines. */
  33                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  34         } else {
  35                 /* Ensure the CPU has control of the memory lines. */
  36                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  37         }
  38 }
  39
  40 static void memreset(int controllers, const struct mem_controller *ctrl)
  41 {
  42         if (is_cpu_pre_c0()) {
  43                 udelay(800);
  44                 /* Set memreset_high */
  45                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  46                 udelay(90);
  47         }
  48 }
  49
  50 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  51
  52 static inline int spd_read_byte(unsigned device, unsigned address)
  53 {
  54         return smbus_read_byte(device, address);
  55 }
  56
  57 #include <northbridge/amd/amdk8/amdk8.h>
  58 #include "northbridge/amd/amdk8/incoherent_ht.c"
  59 #include "northbridge/amd/amdk8/coherent_ht.c"
  60 #include "northbridge/amd/amdk8/raminit.c"
  61 #include "lib/generic_sdram.c"
  62 #include "resourcemap.c"
  63 #include "cpu/amd/dualcore/dualcore.c"
  64 #include <spd.h>
  65 #include "cpu/amd/model_fxx/init_cpus.c"
  66 #include "cpu/amd/model_fxx/fidvid.c"
  67
  68 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  69 {
  70         static const uint16_t spd_addr[] = {
  71                 // first node
  72                 DIMM0, DIMM2, 0, 0,
  73                 DIMM1, DIMM3, 0, 0,
  74                 // second node
  75                 DIMM4, DIMM6, 0, 0,
  76                 DIMM5, DIMM7, 0, 0,
  77         };
  78
  79         struct sys_info *sysinfo = &sysinfo_car;
  80         int needs_reset;
  81         unsigned bsp_apicid = 0;
  82
  83         if (bist == 0)
  84                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
  85
  86         winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  87         console_init();
  88
  89         /* Halt if there was a built in self test failure */
  90         report_bist_failure(bist);
  91
  92         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
  93
  94         setup_mb_resource_map();
  95
  96         printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
  97
  98         setup_coherent_ht_domain(); // routing table and start other core0
  99
 100         wait_all_core0_started();
 101 #if CONFIG_LOGICAL_CPUS
 102         // It is said that we should start core1 after all core0 launched
 103         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 104          * So here need to make sure last core0 is started, esp for two way system,
 105          * (there may be apic id conflicts in that case)
 106          */
 107         start_other_cores();
 108         wait_all_other_cores_started(bsp_apicid);
 109 #endif
 110
 111         /* it will set up chains and store link pair for optimization later */
 112         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 113
 114 #if CONFIG_SET_FIDVID
 115         {
 116                 msr_t msr;
 117                 msr=rdmsr(0xc0010042);
 118                 printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 119         }
 120         enable_fid_change();
 121         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 122         init_fidvid_bsp(bsp_apicid);
 123         // show final fid and vid
 124         {
 125                 msr_t msr;
 126                 msr=rdmsr(0xc0010042);
 127                 printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 128         }
 129 #endif
 130
 131         needs_reset = optimize_link_coherent_ht();
 132         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 133
 134         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 135         if (needs_reset) {
 136                 printk(BIOS_INFO, "ht reset -\n");
 137                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 138         }
 139
 140         allow_all_aps_stop(bsp_apicid);
 141
 142         //It's the time to set ctrl in sysinfo now;
 143         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 144
 145         enable_smbus();
 146
 147 #if 0
 148         dump_smbus_registers();
 149 #endif
 150
 151         memreset_setup();
 152
 153         //do we need apci timer, tsc...., only debug need it for better output
 154         /* all ap stopped? */
 155         init_timer(); // Need to use TMICT to synchronize FID/VID
 156         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 157
 158 #if 0
 159         dump_pci_devices();
 160 #endif
 161
 162         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 163 }