src/mainboard/gigabyte/ga_2761gxdk/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   7  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  */
  23
  24 #include <stdint.h>
  25 #include <string.h>
  26 #include <device/pci_def.h>
  27 #include <device/pci_ids.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <cpu/x86/lapic.h>
  31 #include <pc80/mc146818rtc.h>
  32 #include <console/console.h>
  33 #include <spd.h>
  34 #include <cpu/amd/model_fxx_rev.h>
  35 #include <southbridge/sis/sis966/sis966.h>
  36 #include "southbridge/sis/sis966/early_smbus.c"
  37 #include <northbridge/amd/amdk8/raminit.h>
  38 #include <delay.h>
  39 #include <cpu/x86/lapic.h>
  40 #include "northbridge/amd/amdk8/reset_test.c"
  41 #include <superio/ite/common/ite.h>
  42 #include <superio/ite/it8716f/it8716f.h>
  43 #include <cpu/x86/bist.h>
  44 #include "northbridge/amd/amdk8/debug.c"
  45 #include "northbridge/amd/amdk8/setup_resource_map.c"
  46 #include "southbridge/sis/sis966/early_ctrl.c"
  47
  48 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
  49 #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
  50
  51 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  52 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  53
  54 static inline int spd_read_byte(unsigned device, unsigned address)
  55 {
  56         return smbus_read_byte(device, address);
  57 }
  58
  59 #include <northbridge/amd/amdk8/f.h>
  60 #include "northbridge/amd/amdk8/incoherent_ht.c"
  61 #include "northbridge/amd/amdk8/coherent_ht.c"
  62 #include "northbridge/amd/amdk8/raminit_f.c"
  63 #include "lib/generic_sdram.c"
  64 #include "resourcemap.c"
  65 #include "cpu/amd/dualcore/dualcore.c"
  66
  67 #define SIS966_NUM 1
  68 #define SIS966_USE_NIC 1
  69 #define SIS966_USE_AZA 1
  70
  71 #define SIS966_PCI_E_X_0 0
  72
  73 #define SIS966_MB_SETUP \
  74         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
  75         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
  76         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
  77         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
  78         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
  79         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
  80
  81 #include <southbridge/sis/sis966/early_setup_ss.h>
  82 #include "cpu/amd/model_fxx/init_cpus.c"
  83 #include "cpu/amd/model_fxx/fidvid.c"
  84 #include "northbridge/amd/amdk8/early_ht.c"
  85
  86 static void sio_setup(void)
  87 {
  88         uint32_t dword;
  89         uint8_t byte;
  90
  91         byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b);
  92         byte |= 0x20;
  93         pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
  94
  95         dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0);
  96         dword |= (1<<0);
  97         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
  98
  99         dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4);
 100         dword |= (1<<16);
 101         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
 102 }
 103
 104 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 105 {
 106         static const uint16_t spd_addr [] = {
 107                 // Node 0
 108                 DIMM0, DIMM2, 0, 0,
 109                 DIMM1, DIMM3, 0, 0,
 110                 // Node 1
 111                 DIMM4, DIMM6, 0, 0,
 112                 DIMM5, DIMM7, 0, 0,
 113         };
 114
 115         struct sys_info *sysinfo = &sysinfo_car;
 116         int needs_reset = 0;
 117         unsigned bsp_apicid = 0;
 118
 119         if (!cpu_init_detectedx && boot_cpu()) {
 120                 /* Nothing special needs to be done to find bus 0 */
 121                 /* Allow the HT devices to be found */
 122                 enumerate_ht_chain();
 123                 sio_setup();
 124         }
 125
 126         if (bist == 0)
 127                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 128
 129         ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
 130         ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 131
 132         setup_mb_resource_map();
 133
 134         console_init();
 135
 136         /* Halt if there was a built in self test failure */
 137         report_bist_failure(bist);
 138
 139         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 140
 141         printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 142
 143         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 144         setup_coherent_ht_domain(); // routing table and start other core0
 145
 146         wait_all_core0_started();
 147 #if CONFIG_LOGICAL_CPUS
 148         // It is said that we should start core1 after all core0 launched
 149         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 150          * So here need to make sure last core0 is started, esp for two way system,
 151          * (there may be apic id conflicts in that case)
 152          */
 153         start_other_cores();
 154         wait_all_other_cores_started(bsp_apicid);
 155 #endif
 156
 157         /* it will set up chains and store link pair for optimization later */
 158         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 159
 160 #if CONFIG_SET_FIDVID
 161         {
 162                 msr_t msr;
 163                 msr=rdmsr(0xc0010042);
 164                 printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 165         }
 166         enable_fid_change();
 167         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 168         init_fidvid_bsp(bsp_apicid);
 169         // show final fid and vid
 170         {
 171                 msr_t msr;
 172                 msr=rdmsr(0xc0010042);
 173                 printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 174         }
 175 #endif
 176
 177         needs_reset |= optimize_link_coherent_ht();
 178         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 179
 180         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 181         if (needs_reset) {
 182                 printk(BIOS_INFO, "ht reset -\n");
 183                 soft_reset();
 184         }
 185         allow_all_aps_stop(bsp_apicid);
 186
 187         //It's the time to set ctrl in sysinfo now;
 188         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 189
 190         sis_init_stage1();
 191         enable_smbus();
 192
 193         //do we need apci timer, tsc...., only debug need it for better output
 194         /* all ap stopped? */
 195 //        init_timer(); // Need to use TMICT to synchronize FID/VID
 196
 197         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 198
 199         sis_init_stage2();
 200         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 201 }