src/mainboard/google/volteer/variants/eldrid/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6
   7 /* Pad configuration in ramstage */
   8 static const struct pad_config override_gpio_table[] = {
   9         /* A7  : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
  10         PAD_CFG_GPO(GPP_A7, 1, DEEP),
  11         /* A8  : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
  12         PAD_CFG_GPO(GPP_A8, 0, DEEP),
  13         /* A10 : I2S2_RXD ==> EN_SPKR_PA */
  14         PAD_CFG_GPO(GPP_A10, 1, DEEP),
  15         /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
  16         PAD_CFG_GPO(GPP_A13, 1, DEEP),
  17         /* A15 : USB_OC2# ==> NC */
  18         PAD_NC(GPP_A15, NONE),
  19         /* A16 : USB_OC3# ==> USB_C0_OC_ODL */
  20         PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
  21         /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
  22         PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
  23         /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
  24         PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
  25         /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
  26         PAD_CFG_GPO(GPP_A21, 1, DEEP),
  27         /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
  28         PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
  29
  30         /* B2  : VRALERT# ==> EN_PP3300_SSD */
  31         PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
  32         /* B7  : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */
  33         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
  34         /* B8  : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */
  35         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
  36         /* B9  : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
  37         PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
  38         /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
  39         PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
  40         /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
  41         PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
  42         /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
  43         PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
  44         /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
  45         PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
  46
  47         /* C0  : SMBCLK ==> EN_PP3300_WLAN */
  48         PAD_CFG_GPO(GPP_C0, 1, DEEP),
  49         /* C5  : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */
  50         PAD_CFG_GPI(GPP_C5, NONE, DEEP),
  51         /* C10 : UART0_RTS# ==> USI_RST_L */
  52         PAD_CFG_GPO(GPP_C10, 0, DEEP),
  53         /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
  54         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
  55         /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
  56         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
  57         /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
  58         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
  59         /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
  60         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
  61         /* C20 : UART2_RXD ==> FPMCU_INT_L */
  62         /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */
  63         PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
  64         /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
  65         PAD_CFG_GPO(GPP_C22, 0, DEEP),
  66         /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
  67         PAD_CFG_GPO(GPP_C23, 1, DEEP),
  68
  69         /* D4  : IMGCLKOUT0# ==> CAMMERA_SWITCH */
  70         PAD_CFG_GPI(GPP_D4, NONE, DEEP),
  71         /* D6  : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
  72         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
  73         /* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
  74         PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
  75         /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */
  76         PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
  77         /* D13 : ISH_UART0_RXD ==> NC */
  78         PAD_NC(GPP_D13, NONE),
  79         /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
  80         PAD_CFG_GPO(GPP_D16, 1, DEEP),
  81         /* D17 : ISH_GP4 ==> EN_FCAM_PWR */
  82         PAD_CFG_GPO(GPP_D17, 1, DEEP),
  83
  84         /* E2  : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
  85         PAD_CFG_GPI(GPP_E2, NONE, DEEP),
  86         /* E3  : CPU_GP0 ==> USI_REPORT_EN */
  87         PAD_CFG_GPO(GPP_E3, 1, DEEP),
  88         /* E4  : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
  89         PAD_CFG_GPI(GPP_E4, NONE, DEEP),
  90         /* E6  : THC0_SPI1_RST# ==> GPP_E6_STRAP */
  91         PAD_CFG_GPI(GPP_E6, NONE, DEEP),
  92         /* E7  : CPU_GP1 ==> USI_INT */
  93         PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
  94         /* E8  : SPI1_CS1# ==> SLP_S0IX */
  95         PAD_CFG_GPO(GPP_E8, 0, DEEP),
  96         /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */
  97         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6),
  98         /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
  99         PAD_CFG_GPI(GPP_E11, NONE, DEEP),
 100         /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */
 101         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6),
 102         /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
 103         PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
 104         /* E20 : DDP2_CTRLCLK ==> NC */
 105         PAD_NC(GPP_E20, NONE),
 106         /* E21 : DDP2_CTRLDATA ==> NC */
 107         PAD_NC(GPP_E21, NONE),
 108         /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */
 109         PAD_CFG_GPO(GPP_E22, 1, DEEP),
 110         /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */
 111         PAD_CFG_GPO(GPP_E23, 1, DEEP),
 112
 113         /* F7  : GPPF7_STRAP ==> GPP_F7_STRAP */
 114         PAD_CFG_GPI(GPP_F7, NONE, DEEP),
 115         /* F8  : I2S_MCLK2_INOUT ==> HP_INT_L */
 116         PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH),
 117         /* F10 : GPPF10_STRAP ==> GPP_F10_STRAP */
 118         PAD_CFG_GPI(GPP_F10, NONE, DEEP),
 119         /* F11 : THC1_SPI2_CLK ==> NC */
 120         PAD_NC(GPP_F11, NONE),
 121         /* F12 : GSXDOUT ==> NC */
 122         PAD_NC(GPP_F12, NONE),
 123         /* F13 : GSXDOUT ==> WiFi_DISABLE_L */
 124         PAD_CFG_GPO(GPP_F13, 1, DEEP),
 125
 126         /* H0  : GPPH0_BOOT_STRAP1 */
 127         PAD_CFG_GPI(GPP_H0, NONE, DEEP),
 128         /* H1  : GPPH1_BOOT_STRAP2 */
 129         PAD_CFG_GPI(GPP_H1, NONE, DEEP),
 130         /* H2  : GPPH2_BOOT_STRAP3 */
 131         PAD_CFG_GPI(GPP_H2, NONE, DEEP),
 132         /* H3  : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
 133         PAD_CFG_GPO(GPP_H3, 1, DEEP),
 134         /* H4  : I2C2_SDA ==> NC */
 135         PAD_NC(GPP_H4, NONE),
 136         /* H5  : I2C2_SCL ==> NC */
 137         PAD_NC(GPP_H5, NONE),
 138         /* H10 : SRCCLKREQ4# ==> NC */
 139         PAD_NC(GPP_H10, NONE),
 140         /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
 141         PAD_CFG_GPO(GPP_H11, 1, DEEP),
 142
 143         /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
 144         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
 145         /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
 146         PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
 147         /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
 148         PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
 149         /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
 150         PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
 151         /* R6 : I2S1_TXD ==> I2S1_PCH_TX_SPKR_RX_R */
 152         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
 153         /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM_R */
 154         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
 155
 156         /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK_R */
 157         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
 158         /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA_R */
 159         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
 160         /* S4 : SNDW2_CLK ==> PCH_DMIC_CAM_SCL_R */
 161         PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
 162         /* S5 : SNDW2_DATA ==> PCH_DMIC_CAM_SDA_R */
 163         PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
 164
 165         /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
 166         PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 167 };
 168
 169 /* Early pad configuration in bootblock */
 170 static const struct pad_config early_gpio_table[] = {
 171         /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
 172         PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
 173         /* A17 : DDSP_HPDC ==> MEM_CH_SEL */
 174         PAD_CFG_GPI(GPP_A17, NONE, DEEP),
 175
 176         /* B11 : PMCALERT# ==> PCH_WP_OD */
 177         PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
 178         /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
 179         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 180         /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
 181         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
 182         /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
 183         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 184         /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
 185         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 186
 187         /* C0  : SMBCLK ==> EN_PP3300_WLAN */
 188         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 189         /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
 190         PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
 191         /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
 192         PAD_CFG_GPO(GPP_C22, 0, DEEP),
 193
 194         /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
 195         PAD_CFG_GPO(GPP_D16, 1, DEEP),
 196
 197         /* E12 : SPI1_MISO_IO1 ==> NC */
 198         PAD_NC(GPP_E12, NONE),
 199
 200         /* F11 : THC1_SPI2_CLK ==> NC */
 201         PAD_NC(GPP_F11, NONE),
 202
 203         /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
 204         PAD_CFG_GPO(GPP_H11, 1, DEEP),
 205 };
 206
 207 const struct pad_config *variant_override_gpio_table(size_t *num)
 208 {
 209         *num = ARRAY_SIZE(override_gpio_table);
 210         return override_gpio_table;
 211 }
 212
 213 const struct pad_config *variant_early_gpio_table(size_t *num)
 214 {
 215         *num = ARRAY_SIZE(early_gpio_table);
 216         return early_gpio_table;
 217 }