src/soc/rockchip/rk3288/hdmi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) Rockchip, Inc.
   5  * Copyright (C) Freescale Semiconductor, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 /*
  19  * Designware High-Definition Multimedia Interface (HDMI) driveG
  20  */
  21
  22 #include <device/mmio.h>
  23 #include <console/console.h>
  24 #include <delay.h>
  25 #include <edid.h>
  26 #include <gpio.h>
  27 #include <stdint.h>
  28 #include <soc/addressmap.h>
  29 #include <soc/hdmi.h>
  30 #include <soc/grf.h>
  31 #include <soc/vop.h>
  32 #include <timer.h>
  33
  34 #include "chip.h"
  35
  36 #define AUDIO_SAMPLERATE_DEFAULT        (48*KHz)
  37
  38 #define hdmi_debug(x...)        do { if (0) printk(BIOS_DEBUG, x); } while (0)
  39
  40 struct rk3288_hdmi_regs * const hdmi_regs = (void *)HDMI_TX_BASE;
  41
  42 struct tmds_n_cts {
  43         u32 tmds;
  44         u32 cts;
  45         u32 n;
  46 };
  47
  48 static const struct tmds_n_cts n_cts_table[] = {
  49         {
  50                 .tmds = 25175, .n = 6144, .cts = 25175,
  51         }, {
  52                 .tmds = 25200, .n = 6144, .cts = 25200,
  53         }, {
  54                 .tmds = 27000, .n = 6144, .cts = 27000,
  55         }, {
  56                 .tmds = 27027, .n = 6144, .cts = 27027,
  57         }, {
  58                 .tmds = 40000, .n = 6144, .cts = 40000,
  59         }, {
  60                 .tmds = 54000, .n = 6144, .cts = 54000,
  61         }, {
  62                 .tmds = 54054, .n = 6144, .cts = 54054,
  63         }, {
  64                 .tmds = 65000, .n = 6144, .cts = 65000,
  65         }, {
  66                 .tmds = 74176, .n = 11648, .cts = 140625,
  67         }, {
  68                 .tmds = 74250, .n = 6144, .cts = 74250,
  69         }, {
  70                 .tmds = 83500, .n = 6144, .cts = 83500,
  71         }, {
  72                 .tmds = 106500, .n = 6144, .cts = 106500,
  73         }, {
  74                 .tmds = 108000, .n = 6144, .cts = 108000,
  75         }, {
  76                 .tmds = 148352, .n = 5824, .cts = 140625,
  77         }, {
  78                 .tmds = 148500, .n = 6144, .cts = 148500,
  79         }, {
  80                 .tmds = 297000, .n = 5120, .cts = 247500,
  81         }
  82 };
  83
  84 struct hdmi_mpll_config {
  85         u64 mpixelclock;
  86         /* Mode of Operation and PLL Dividers Control Register */
  87         u32 cpce;
  88         /* PLL Gmp Control Register */
  89         u32 gmp;
  90         /* PLL Current COntrol Register */
  91         u32 curr;
  92 };
  93
  94 struct hdmi_phy_config {
  95         u64 mpixelclock;
  96         u32 sym_ctr;    /* clock symbol and transmitter control */
  97         u32 term;       /* transmission termination value */
  98         u32 vlev_ctr;   /* voltage level control */
  99 };
 100
 101 static const struct hdmi_phy_config rockchip_phy_config[] = {
 102         {
 103                 .mpixelclock = 74250,
 104                 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
 105         }, {
 106                 .mpixelclock = 148500,
 107                 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
 108         }, {
 109                 .mpixelclock = 297000,
 110                 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
 111         }, {
 112                 .mpixelclock = ~0ul,
 113                 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
 114         }
 115 };
 116
 117 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
 118         {
 119                 .mpixelclock = 40000,
 120                 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
 121         }, {
 122                 .mpixelclock = 65000,
 123                 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
 124         }, {
 125                 .mpixelclock = 66000,
 126                 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
 127         }, {
 128                 .mpixelclock = 83500,
 129                 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
 130         }, {
 131                 .mpixelclock = 146250,
 132                 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
 133         }, {
 134                 .mpixelclock = 148500,
 135                 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
 136         }, {
 137                 .mpixelclock = ~0ul,
 138                 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
 139         }
 140 };
 141
 142 static const u32 csc_coeff_default[3][4] = {
 143         { 0x2000, 0x0000, 0x0000, 0x0000 },
 144         { 0x0000, 0x2000, 0x0000, 0x0000 },
 145         { 0x0000, 0x0000, 0x2000, 0x0000 }
 146 };
 147
 148 static void hdmi_set_clock_regenerator(u32 n, u32 cts)
 149 {
 150         u8 cts3;
 151         u8 n3;
 152
 153         /* first set ncts_atomic_write (if present) */
 154         n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
 155         write32(&hdmi_regs->aud_n3, n3);
 156
 157         /* set cts_manual (if present) */
 158         cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
 159
 160         cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
 161         cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
 162
 163         /* write cts values; cts3 must be written first */
 164         write32(&hdmi_regs->aud_cts3, cts3);
 165         write32(&hdmi_regs->aud_cts2, (cts >> 8) & 0xff);
 166         write32(&hdmi_regs->aud_cts1, cts & 0xff);
 167
 168         /* write n values; n1 must be written last */
 169         n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
 170         write32(&hdmi_regs->aud_n3, n3);
 171         write32(&hdmi_regs->aud_n2, (n >> 8) & 0xff);
 172         write32(&hdmi_regs->aud_n1, n & 0xff);
 173
 174         write32(&hdmi_regs->aud_inputclkfs, HDMI_AUD_INPUTCLKFS_128);
 175 }
 176
 177 static int hdmi_lookup_n_cts(u32 pixel_clk)
 178 {
 179         int i;
 180
 181         for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
 182                 if (pixel_clk <= n_cts_table[i].tmds)
 183                         break;
 184
 185         if (i >= ARRAY_SIZE(n_cts_table))
 186                 return -1;
 187
 188         return i;
 189 }
 190
 191 static void hdmi_audio_set_samplerate(u32 pixel_clk)
 192 {
 193         u32 clk_n, clk_cts;
 194         int index;
 195
 196         index = hdmi_lookup_n_cts(pixel_clk);
 197         if (index == -1) {
 198                 hdmi_debug("audio not supported for pixel clk %d\n", pixel_clk);
 199                 return;
 200         }
 201
 202         clk_n = n_cts_table[index].n;
 203         clk_cts = n_cts_table[index].cts;
 204         hdmi_set_clock_regenerator(clk_n, clk_cts);
 205 }
 206
 207 /*
 208  * this submodule is responsible for the video data synchronization.
 209  * for example, for rgb 4:4:4 input, the data map is defined as
 210  *                      pin{47~40} <==> r[7:0]
 211  *                      pin{31~24} <==> g[7:0]
 212  *                      pin{15~8}  <==> b[7:0]
 213  */
 214 static void hdmi_video_sample(void)
 215 {
 216         u32 color_format = 0x01;
 217         u8 val;
 218
 219         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 220               ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 221               HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 222
 223         write32(&hdmi_regs->tx_invid0, val);
 224
 225         /* enable tx stuffing: when de is inactive, fix the output data to 0 */
 226         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 227               HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 228               HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 229         write32(&hdmi_regs->tx_instuffing, val);
 230         write32(&hdmi_regs->tx_gydata0, 0x0);
 231         write32(&hdmi_regs->tx_gydata1, 0x0);
 232         write32(&hdmi_regs->tx_rcrdata0, 0x0);
 233         write32(&hdmi_regs->tx_rcrdata1, 0x0);
 234         write32(&hdmi_regs->tx_bcbdata0, 0x0);
 235         write32(&hdmi_regs->tx_bcbdata1, 0x0);
 236 }
 237
 238 static void hdmi_update_csc_coeffs(void)
 239 {
 240         u32 i, j;
 241         u32 csc_scale = 1;
 242
 243         /* the csc registers are sequential, alternating msb then lsb */
 244         for (i = 0; i < ARRAY_SIZE(csc_coeff_default); i++) {
 245                 for (j = 0; j < ARRAY_SIZE(csc_coeff_default[0]); j++) {
 246                         u32 coeff = csc_coeff_default[i][j];
 247                         write32(&hdmi_regs->csc_coef[i][j].msb, coeff >> 8);
 248                         write32(&hdmi_regs->csc_coef[i][j].lsb, coeff & 0xff);
 249                 }
 250         }
 251
 252         clrsetbits32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 253                      csc_scale);
 254 }
 255
 256 static void hdmi_video_csc(void)
 257 {
 258         u32 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 259         u32 interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 260
 261         /* configure the csc registers */
 262         write32(&hdmi_regs->csc_cfg, interpolation);
 263         clrsetbits32(&hdmi_regs->csc_scale,
 264                      HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth);
 265
 266         hdmi_update_csc_coeffs();
 267 }
 268
 269 static void hdmi_video_packetize(void)
 270 {
 271         u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 272         u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
 273         u32 color_depth = 0;
 274         u8 val, vp_conf;
 275
 276         /* set the packetizer registers */
 277         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 278                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 279                 ((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 280                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 281         write32(&hdmi_regs->vp_pr_cd, val);
 282
 283         clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK,
 284                      HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
 285
 286         /* data from pixel repeater block */
 287         vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 288                   HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 289
 290         clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK |
 291                      HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
 292
 293         clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
 294                      1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
 295
 296         write32(&hdmi_regs->vp_remap, remap_size);
 297
 298         vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 299                   HDMI_VP_CONF_PP_EN_DISABLE |
 300                   HDMI_VP_CONF_YCC422_EN_DISABLE;
 301
 302         clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK |
 303                      HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
 304                      vp_conf);
 305
 306         clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK |
 307                      HDMI_VP_STUFF_YCC422_STUFFING_MASK,
 308                      HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 309                      HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
 310
 311         clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 312                      output_select);
 313 }
 314
 315 static inline void hdmi_phy_test_clear(u8 bit)
 316 {
 317         clrsetbits32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK,
 318                      bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
 319 }
 320
 321 static int hdmi_phy_wait_i2c_done(u32 msec)
 322 {
 323         struct stopwatch phyi2c_done;
 324         u32 val;
 325
 326         stopwatch_init_msecs_expire(&phyi2c_done, msec);
 327         do {
 328                 val = read32(&hdmi_regs->ih_i2cmphy_stat0);
 329                 if (val & 0x3) {
 330                         write32(&hdmi_regs->ih_i2cmphy_stat0, val);
 331                         return 0;
 332                 }
 333
 334                 udelay(100);
 335         } while (!stopwatch_expired(&phyi2c_done));
 336
 337         return 1;
 338 }
 339
 340 static void hdmi_phy_i2c_write(u16 data, u8 addr)
 341 {
 342         write32(&hdmi_regs->ih_i2cmphy_stat0, 0xff);
 343         write32(&hdmi_regs->phy_i2cm_address_addr, addr);
 344         write32(&hdmi_regs->phy_i2cm_datao_1_addr, (u8)(data >> 8));
 345         write32(&hdmi_regs->phy_i2cm_datao_0_addr, (u8)(data >> 0));
 346         write32(&hdmi_regs->phy_i2cm_operation_addr,
 347                 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE);
 348
 349         hdmi_phy_wait_i2c_done(1000);
 350 }
 351
 352 static void hdmi_phy_enable_power(u8 enable)
 353 {
 354         clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK,
 355                      enable << HDMI_PHY_CONF0_PDZ_OFFSET);
 356 }
 357
 358 static void hdmi_phy_enable_tmds(u8 enable)
 359 {
 360         clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK,
 361                      enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
 362 }
 363
 364 static void hdmi_phy_enable_spare(u8 enable)
 365 {
 366         clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK,
 367                      enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
 368 }
 369
 370 static void hdmi_phy_gen2_pddq(u8 enable)
 371 {
 372         clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
 373                      enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
 374 }
 375
 376 static void hdmi_phy_gen2_txpwron(u8 enable)
 377 {
 378         clrsetbits32(&hdmi_regs->phy_conf0,
 379                      HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
 380                      enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
 381 }
 382
 383 static void hdmi_phy_sel_data_en_pol(u8 enable)
 384 {
 385         clrsetbits32(&hdmi_regs->phy_conf0,
 386                      HDMI_PHY_CONF0_SELDATAENPOL_MASK,
 387                      enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
 388 }
 389
 390 static void hdmi_phy_sel_interface_control(u8 enable)
 391 {
 392         clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK,
 393                      enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
 394 }
 395
 396 static int hdmi_phy_configure(u32 mpixelclock)
 397 {
 398         struct stopwatch pll_ready;
 399         u8 i, val;
 400
 401         write32(&hdmi_regs->mc_flowctrl,
 402                 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS);
 403
 404         /* gen2 tx power off */
 405         hdmi_phy_gen2_txpwron(0);
 406
 407         /* gen2 pddq */
 408         hdmi_phy_gen2_pddq(1);
 409
 410         /* phy reset */
 411         write32(&hdmi_regs->mc_phyrstz, HDMI_MC_PHYRSTZ_DEASSERT);
 412         write32(&hdmi_regs->mc_phyrstz, HDMI_MC_PHYRSTZ_ASSERT);
 413         write32(&hdmi_regs->mc_heacphy_rst, HDMI_MC_HEACPHY_RST_ASSERT);
 414
 415         hdmi_phy_test_clear(1);
 416         write32(&hdmi_regs->phy_i2cm_slave_addr,
 417                 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
 418         hdmi_phy_test_clear(0);
 419
 420         /* pll/mpll cfg - always match on final entry */
 421         for (i = 0; rockchip_mpll_cfg[i].mpixelclock != (~0ul); i++)
 422                 if (mpixelclock <= rockchip_mpll_cfg[i].mpixelclock)
 423                         break;
 424
 425         hdmi_phy_i2c_write(rockchip_mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
 426         hdmi_phy_i2c_write(rockchip_mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
 427         hdmi_phy_i2c_write(rockchip_mpll_cfg[i].curr, PHY_PLLCURRCTRL);
 428
 429         hdmi_phy_i2c_write(0x0000, PHY_PLLPHBYCTRL);
 430         hdmi_phy_i2c_write(0x0006, PHY_PLLCLKBISTPHASE);
 431
 432         for (i = 0; rockchip_phy_config[i].mpixelclock != (~0ul); i++)
 433                 if (mpixelclock <= rockchip_phy_config[i].mpixelclock)
 434                         break;
 435
 436         /*
 437          * resistance term 133ohm cfg
 438          * preemp cgf 0.00
 439          * tx/ck lvl 10
 440          */
 441         hdmi_phy_i2c_write(rockchip_phy_config[i].term, PHY_TXTERM);
 442         hdmi_phy_i2c_write(rockchip_phy_config[i].sym_ctr, PHY_CKSYMTXCTRL);
 443         hdmi_phy_i2c_write(rockchip_phy_config[i].vlev_ctr, PHY_VLEVCTRL);
 444
 445         /* remove clk term */
 446         hdmi_phy_i2c_write(0x8000, PHY_CKCALCTRL);
 447
 448         hdmi_phy_enable_power(1);
 449
 450         /* toggle tmds enable */
 451         hdmi_phy_enable_tmds(0);
 452         hdmi_phy_enable_tmds(1);
 453
 454         /* gen2 tx power on */
 455         hdmi_phy_gen2_txpwron(1);
 456         hdmi_phy_gen2_pddq(0);
 457
 458         hdmi_phy_enable_spare(1);
 459
 460         /* wait for phy pll lock */
 461         stopwatch_init_msecs_expire(&pll_ready, 5);
 462         do {
 463                 val = read32(&hdmi_regs->phy_stat0);
 464                 if (!(val & HDMI_PHY_TX_PHY_LOCK))
 465                         return 0;
 466
 467                 udelay(100);
 468         } while (!stopwatch_expired(&pll_ready));
 469
 470         return -1;
 471 }
 472
 473 static int hdmi_phy_init(u32 mpixelclock)
 474 {
 475         int i, ret;
 476
 477         /* hdmi phy spec says to do the phy initialization sequence twice */
 478         for (i = 0; i < 2; i++) {
 479                 hdmi_phy_sel_data_en_pol(1);
 480                 hdmi_phy_sel_interface_control(0);
 481                 hdmi_phy_enable_tmds(0);
 482                 hdmi_phy_enable_power(0);
 483
 484                 /* enable csc */
 485                 ret = hdmi_phy_configure(mpixelclock);
 486                 if (ret) {
 487                         hdmi_debug("hdmi phy config failure %d\n", ret);
 488                         return ret;
 489                 }
 490         }
 491
 492         return 0;
 493 }
 494
 495 static void hdmi_av_composer(const struct edid *edid)
 496 {
 497         u8 mdataenablepolarity = 1;
 498         u8 inv_val;
 499
 500         /* set up hdmi_fc_invidconf */
 501         inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
 502
 503         inv_val |= ((edid->mode.pvsync == '+') ?
 504                    HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
 505                    HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
 506
 507         inv_val |= ((edid->mode.phsync == '+') ?
 508                    HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
 509                    HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
 510
 511         inv_val |= (mdataenablepolarity ?
 512                    HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
 513                    HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
 514
 515         inv_val |= (edid->hdmi_monitor_detected ?
 516                    HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
 517                    HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
 518
 519         inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
 520
 521         inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
 522
 523         write32(&hdmi_regs->fc_invidconf, inv_val);
 524
 525         /* set up horizontal active pixel width */
 526         write32(&hdmi_regs->fc_inhactv1, edid->mode.ha >> 8);
 527         write32(&hdmi_regs->fc_inhactv0, edid->mode.ha);
 528
 529         /* set up vertical active lines */
 530         write32(&hdmi_regs->fc_invactv1, edid->mode.va >> 8);
 531         write32(&hdmi_regs->fc_invactv0, edid->mode.va);
 532
 533         /* set up horizontal blanking pixel region width */
 534         write32(&hdmi_regs->fc_inhblank1, edid->mode.hbl >> 8);
 535         write32(&hdmi_regs->fc_inhblank0, edid->mode.hbl);
 536
 537         /* set up vertical blanking pixel region width */
 538         write32(&hdmi_regs->fc_invblank, edid->mode.vbl);
 539
 540         /* set up hsync active edge delay width (in pixel clks) */
 541         write32(&hdmi_regs->fc_hsyncindelay1, edid->mode.hso >> 8);
 542         write32(&hdmi_regs->fc_hsyncindelay0, edid->mode.hso);
 543
 544         /* set up vsync active edge delay (in lines) */
 545         write32(&hdmi_regs->fc_vsyncindelay, edid->mode.vso);
 546
 547         /* set up hsync active pulse width (in pixel clks) */
 548         write32(&hdmi_regs->fc_hsyncinwidth1, edid->mode.hspw >> 8);
 549         write32(&hdmi_regs->fc_hsyncinwidth0, edid->mode.hspw);
 550
 551         /* set up vsync active edge delay (in lines) */
 552         write32(&hdmi_regs->fc_vsyncinwidth, edid->mode.vspw);
 553 }
 554
 555 /* hdmi initialization step b.4 */
 556 static void hdmi_enable_video_path(void)
 557 {
 558         u8 clkdis;
 559
 560         /* control period minimum duration */
 561         write32(&hdmi_regs->fc_ctrldur, 12);
 562         write32(&hdmi_regs->fc_exctrldur, 32);
 563         write32(&hdmi_regs->fc_exctrlspac, 1);
 564
 565         /* set to fill tmds data channels */
 566         write32(&hdmi_regs->fc_ch0pream, 0x0b);
 567         write32(&hdmi_regs->fc_ch1pream, 0x16);
 568         write32(&hdmi_regs->fc_ch2pream, 0x21);
 569
 570         /* enable pixel clock and tmds data path */
 571         clkdis = 0x7f;
 572         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
 573         write32(&hdmi_regs->mc_clkdis, clkdis);
 574
 575         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
 576         write32(&hdmi_regs->mc_clkdis, clkdis);
 577
 578         clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 579         write32(&hdmi_regs->mc_clkdis, clkdis);
 580 }
 581
 582 /* workaround to clear the overflow condition */
 583 static void hdmi_clear_overflow(void)
 584 {
 585         u8 val, count;
 586
 587         /* tmds software reset */
 588         write32(&hdmi_regs->mc_swrstz, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ);
 589
 590         val = read32(&hdmi_regs->fc_invidconf);
 591
 592         for (count = 0; count < 4; count++)
 593                 write32(&hdmi_regs->fc_invidconf, val);
 594 }
 595
 596 static void hdmi_audio_set_format(void)
 597 {
 598         write32(&hdmi_regs->aud_conf0,
 599                 HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0);
 600
 601         write32(&hdmi_regs->aud_conf1,
 602                 HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
 603                 HDMI_AUD_CONF1_I2S_WIDTH_16BIT);
 604
 605         write32(&hdmi_regs->aud_conf2, 0x00);
 606 }
 607
 608 static void hdmi_audio_fifo_reset(void)
 609 {
 610         write32(&hdmi_regs->mc_swrstz, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ);
 611         write32(&hdmi_regs->aud_conf0, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST);
 612
 613         write32(&hdmi_regs->aud_int, 0x00);
 614         write32(&hdmi_regs->aud_int1, 0x00);
 615 }
 616
 617 static int hdmi_setup(const struct edid *edid)
 618 {
 619         int ret;
 620
 621         hdmi_debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
 622                    edid->mode.pixel_clock, edid->mode.ha, edid->mode.va);
 623
 624         hdmi_av_composer(edid);
 625
 626         ret = hdmi_phy_init(edid->mode.pixel_clock);
 627         if (ret)
 628                 return ret;
 629
 630         hdmi_enable_video_path();
 631
 632         hdmi_audio_fifo_reset();
 633         hdmi_audio_set_format();
 634         hdmi_audio_set_samplerate(edid->mode.pixel_clock);
 635
 636         hdmi_video_packetize();
 637         hdmi_video_csc();
 638         hdmi_video_sample();
 639
 640         hdmi_clear_overflow();
 641
 642         return 0;
 643 }
 644
 645 static void hdmi_init_interrupt(void)
 646 {
 647         u8 ih_mute;
 648
 649         /*
 650          * boot up defaults are:
 651          * hdmi_ih_mute   = 0x03 (disabled)
 652          * hdmi_ih_mute_* = 0x00 (enabled)
 653          *
 654          * disable top level interrupt bits in hdmi block
 655          */
 656         ih_mute = read32(&hdmi_regs->ih_mute) |
 657                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
 658                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
 659
 660         write32(&hdmi_regs->ih_mute, ih_mute);
 661
 662         /* enable i2c master done irq */
 663         write32(&hdmi_regs->i2cm_int, ~0x04);
 664
 665         /* enable i2c client nack % arbitration error irq */
 666         write32(&hdmi_regs->i2cm_ctlint, ~0x44);
 667
 668         /* enable phy i2cm done irq */
 669         write32(&hdmi_regs->phy_i2cm_int_addr, HDMI_PHY_I2CM_INT_ADDR_DONE_POL);
 670
 671         /* enable phy i2cm nack & arbitration error irq */
 672         write32(&hdmi_regs->phy_i2cm_ctlint_addr,
 673                 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
 674                 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL);
 675
 676         /* enable cable hot plug irq */
 677         write32(&hdmi_regs->phy_mask0, (u8)~HDMI_PHY_HPD);
 678
 679         /* clear hotplug interrupts */
 680         write32(&hdmi_regs->ih_phy_stat0, HDMI_IH_PHY_STAT0_HPD);
 681 }
 682
 683 static u8 hdmi_get_plug_in_status(void)
 684 {
 685         u8 val = read32(&hdmi_regs->phy_stat0) & HDMI_PHY_HPD;
 686
 687         return !!(val);
 688 }
 689
 690 static int hdmi_wait_for_hpd(void)
 691 {
 692         struct stopwatch hpd;
 693
 694         stopwatch_init_msecs_expire(&hpd, 30000);
 695         do {
 696                 if (hdmi_get_plug_in_status())
 697                         return 0;
 698                 udelay(100);
 699         } while (!stopwatch_expired(&hpd));
 700
 701         return -1;
 702 }
 703
 704 static int hdmi_ddc_wait_i2c_done(int msec)
 705 {
 706         struct stopwatch ddci2c_done;
 707         u32 val;
 708
 709         stopwatch_init_msecs_expire(&ddci2c_done, msec);
 710         do {
 711                 val = read32(&hdmi_regs->ih_i2cm_stat0);
 712                 if (val & 0x2) {
 713                         write32(&hdmi_regs->ih_i2cm_stat0, val);
 714                         return 0;
 715                 }
 716
 717                 udelay(100);
 718         } while (!stopwatch_expired(&ddci2c_done));
 719
 720         return 1;
 721 }
 722
 723 static void hdmi_ddc_reset(void)
 724 {
 725         clrsetbits32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ,
 726                      HDMI_I2CM_SOFTRSTZ);
 727 }
 728
 729 static int hdmi_read_edid(int block, u8 *buff)
 730 {
 731         int shift = (block % 2) * 0x80;
 732         int edid_read_err = 0;
 733         u32 trytime = 5;
 734         u32 n, j, val;
 735
 736         /* set ddc i2c clk which devided from ddc_clk to 100khz */
 737         write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a);
 738         write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d);
 739         clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE,
 740                         HDMI_I2CM_DIV_STD_MODE);
 741
 742         write32(&hdmi_regs->i2cm_slave, HDMI_I2CM_SLAVE_DDC_ADDR);
 743         write32(&hdmi_regs->i2cm_segaddr, HDMI_I2CM_SEGADDR_DDC);
 744         write32(&hdmi_regs->i2cm_segptr, block >> 1);
 745
 746         while (trytime--) {
 747                 edid_read_err = 0;
 748
 749                 for (n = 0; n < HDMI_EDID_BLOCK_SIZE/8; n++) {
 750                         write32(&hdmi_regs->i2cmess, shift + 8 * n);
 751
 752                         if (block == 0)
 753                                 clrsetbits32(&hdmi_regs->i2cm_operation,
 754                                              HDMI_I2CM_OPT_RD8,
 755                                              HDMI_I2CM_OPT_RD8);
 756                         else
 757                                 clrsetbits32(&hdmi_regs->i2cm_operation,
 758                                              HDMI_I2CM_OPT_RD8_EXT,
 759                                              HDMI_I2CM_OPT_RD8_EXT);
 760
 761                         if (hdmi_ddc_wait_i2c_done(10)) {
 762                                 hdmi_ddc_reset();
 763                                 edid_read_err = 1;
 764                                 break;
 765                         }
 766
 767                         for (j = 0; j < 8; j++) {
 768                                 val = read32(&hdmi_regs->i2cm_buf0 + j);
 769                                 buff[8 * n + j] = val;
 770                         }
 771                 }
 772
 773                 if (!edid_read_err)
 774                         break;
 775         }
 776
 777         return edid_read_err;
 778 }
 779
 780 int rk_hdmi_get_edid(struct edid *edid)
 781 {
 782         u8 edid_buf[HDMI_EDID_BLOCK_SIZE * 2];
 783         u32 edid_size = HDMI_EDID_BLOCK_SIZE;
 784         gpio_t hdmi_i2c_sda = GPIO(7, C, 3);
 785         gpio_t hdmi_i2c_scl = GPIO(7, C, 4);
 786         int ret;
 787
 788         /* If SDA is low, try to clock once to fix it */
 789         gpio_input_pullup(hdmi_i2c_sda);
 790         if (gpio_get(hdmi_i2c_sda) == 0) {
 791                 gpio_output(hdmi_i2c_scl, 0);
 792                 udelay(1000);
 793                 gpio_input_pullup(hdmi_i2c_scl);
 794                 udelay(1000);
 795         }
 796
 797         /* HDMI I2C */
 798         write32(&rk3288_grf->iomux_i2c5sda, IOMUX_HDMI_EDP_I2C_SDA);
 799         write32(&rk3288_grf->iomux_i2c5scl, IOMUX_HDMI_EDP_I2C_SCL);
 800
 801         ret = hdmi_read_edid(0, edid_buf);
 802         if (ret) {
 803                 hdmi_debug("failed to read edid.\n");
 804                 return -1;
 805         }
 806
 807         if (edid_buf[0x7e] != 0) {
 808                 hdmi_read_edid(1, edid_buf + HDMI_EDID_BLOCK_SIZE);
 809                 edid_size += HDMI_EDID_BLOCK_SIZE;
 810         }
 811
 812         /* Assume usage of HDMI implies an external display in which case
 813          * we should be lenient about errors that the EDID decoder finds. */
 814         if (decode_edid(edid_buf, edid_size, edid) != EDID_CONFORMANT)
 815                 hdmi_debug("failed to decode edid.\n");
 816
 817         /* Try 480p for best compatibility. */
 818         if (set_display_mode(edid, EDID_MODE_640x480_60Hz))
 819                 hdmi_debug("failed to set mode to 640x480@60Hz\n");
 820
 821         return 0;
 822 }
 823
 824 int rk_hdmi_enable(const struct edid *edid)
 825 {
 826         hdmi_setup(edid);
 827
 828         return 0;
 829 }
 830
 831 int rk_hdmi_init(u32 vop_id)
 832 {
 833         int ret;
 834         u32 val;
 835
 836         /* hdmi source select hdmi controller */
 837         write32(&rk3288_grf->soc_con6, RK_SETBITS(1 << 15));
 838
 839         /* hdmi data from vop id */
 840         val = (vop_id == 1) ? RK_SETBITS(1 << 4) : RK_CLRBITS(1 << 4);
 841         write32(&rk3288_grf->soc_con6, val);
 842
 843         ret = hdmi_wait_for_hpd();
 844         if (ret < 0) {
 845                 hdmi_debug("hdmi can not get hpd signal\n");
 846                 return -1;
 847         }
 848
 849         hdmi_init_interrupt();
 850
 851         hdmi_debug("hdmi init success\n");
 852
 853         return 0;
 854 }