src/mainboard/via/vt8454c/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22 #include <stdint.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <arch/romcc_io.h>
  28 #include <arch/hlt.h>
  29 #include <console/console.h>
  30 #include <lib.h>
  31 #include "northbridge/via/cx700/raminit.h"
  32 #include "cpu/x86/bist.h"
  33 #include "pc80/udelay_io.c"
  34 #include "lib/delay.c"
  35 #include "northbridge/via/cx700/early_smbus.c"
  36 #include "lib/debug.c"
  37 #include "northbridge/via/cx700/early_serial.c"
  38 #include "northbridge/via/cx700/raminit.c"
  39 #include <spd.h>
  40
  41 static void enable_mainboard_devices(void)
  42 {
  43         device_t dev;
  44
  45         dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
  46         if (dev == PCI_DEV_INVALID) {
  47                 die("LPC bridge not found!!!\n");
  48         }
  49         // Disable GP3
  50         pci_write_config8(dev, 0x98, 0x00);
  51
  52         // Disable mc97
  53         pci_write_config8(dev, 0x50, 0x80);
  54
  55         // Disable internal KBC Configuration
  56         pci_write_config8(dev, 0x51, 0x2d);
  57         pci_write_config8(dev, 0x58, 0x42);
  58         pci_write_config8(dev, 0x59, 0x80);
  59         pci_write_config8(dev, 0x5b, 0x01);
  60
  61         // Enable P2P Bridge Header for External PCI BUS.
  62         dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0);
  63         if (dev == PCI_DEV_INVALID) {
  64                 die("P2P bridge not found!!!\n");
  65         }
  66         pci_write_config8(dev, 0x4f, 0x41);
  67
  68         // Switch SATA to non-RAID mode
  69         dev = pci_locate_device(PCI_ID(0x1106, 0x0581), 0);
  70         if (dev != PCI_DEV_INVALID) {
  71                 pci_write_config16(dev, 0xBA, 0x5324);
  72         }
  73 }
  74
  75 static void enable_shadow_ram(const struct mem_controller *ctrl)
  76 {
  77         u8 shadowreg;
  78
  79         pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a);
  80
  81         /* 0xf0000-0xfffff - ACPI tables */
  82         shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
  83         shadowreg |= 0x30;
  84         pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
  85 }
  86
  87 void main(unsigned long bist)
  88 {
  89         /* Set statically so it should work with cx700 as well */
  90         static const struct mem_controller cx700[] = {
  91                 {
  92                         .channel0 = {DIMM0, DIMM1},
  93                 },
  94         };
  95
  96         enable_smbus();
  97
  98         enable_cx700_serial();
  99         console_init();
 100
 101         /* Halt if there was a built in self test failure */
 102         report_bist_failure(bist);
 103
 104         enable_mainboard_devices();
 105
 106         /* Allows access to all northbridge devices */
 107         pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
 108
 109         sdram_set_registers(cx700);
 110         enable_shadow_ram(cx700);
 111         sdram_enable(cx700);
 112 }