src/mainboard/via/epia/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <arch/hlt.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "northbridge/via/vt8601/raminit.h"
  10 #include "cpu/x86/mtrr/earlymtrr.c"
  11 #include "cpu/x86/bist.h"
  12 #include "pc80/udelay_io.c"
  13 #include "lib/delay.c"
  14 #include "lib/debug.c"
  15 #include "southbridge/via/vt8231/early_smbus.c"
  16 #include "southbridge/via/vt8231/early_serial.c"
  17 #include "southbridge/via/vt8231/enable_rom.c"
  18
  19 static inline int spd_read_byte(unsigned device, unsigned address)
  20 {
  21         return smbus_read_byte(device, address);
  22 }
  23
  24 #include "northbridge/via/vt8601/raminit.c"
  25
  26 static void enable_mainboard_devices(void)
  27 {
  28         device_t dev;
  29         /* dev 0 for southbridge */
  30
  31         dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
  32
  33         if (dev == PCI_DEV_INVALID)
  34                 die("Southbridge not found!!!\n");
  35
  36         pci_write_config8(dev, 0x50, 7);
  37         pci_write_config8(dev, 0x51, 0xff);
  38 #if 0
  39         // This early setup switches IDE into compatibility mode before PCI gets
  40         // a chance to assign I/Os
  41         //   movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
  42         //   movb    $0x09, %dl
  43         //   movb    $0x00, %dl
  44         //   PCI_WRITE_CONFIG_BYTE
  45         //
  46 #endif
  47         /* we do this here as in V2, we can not yet do raw operations
  48          * to pci!
  49          */
  50         /* changed this to work correctly on later revisions of LB.
  51         * The original dev += 0x100; stopped working. It also appears
  52         * that if this is not set here, but in ide_init() only, the IDE
  53         * does not work at all. I assume it needs to be set before something else,
  54         * possibly before enabling the IDE peripheral, or it is a timing issue.
  55         * Ben Hewson 29 Apr 2007.
  56         */
  57
  58         dev = pci_locate_device(PCI_ID(0x1106,0x0571), 0);
  59         pci_write_config8(dev, 0x42, 0);
  60 }
  61
  62 static void enable_shadow_ram(void)
  63 {
  64         device_t dev = 0;
  65         unsigned char shadowreg;
  66
  67         shadowreg = pci_read_config8(dev, 0x63);
  68         /* 0xf0000-0xfffff */
  69         shadowreg |= 0x30;
  70         pci_write_config8(dev, 0x63, shadowreg);
  71 }
  72
  73 static void main(unsigned long bist)
  74 {
  75         if (bist == 0)
  76                 early_mtrr_init();
  77
  78         enable_vt8231_serial();
  79         console_init();
  80
  81         /* Halt if there was a built in self test failure */
  82         report_bist_failure(bist);
  83
  84         vt8231_enable_rom();
  85         enable_mainboard_devices();
  86         enable_smbus();
  87         enable_shadow_ram();
  88
  89         /*
  90           this is way more generic than we need.
  91           sdram_initialize(ARRAY_SIZE(cpu), cpu);
  92         */
  93         sdram_set_registers((const struct mem_controller *) 0);
  94         sdram_set_spd_registers((const struct mem_controller *) 0);
  95         sdram_enable(0, (const struct mem_controller *) 0);
  96 }