src/mainboard/via/epia-n/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 VIA Technologies, Inc.
   5  * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #include <stdint.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <arch/romcc_io.h>
  28 #include <arch/hlt.h>
  29 #include <console/console.h>
  30 #include "northbridge/via/cn400/raminit.h"
  31 #include "cpu/x86/mtrr/earlymtrr.c"
  32 #include "cpu/x86/bist.h"
  33 #include "pc80/udelay_io.c"
  34 #include "lib/delay.c"
  35 #include "cpu/x86/lapic/boot_cpu.c"
  36 #include "southbridge/via/vt8237r/early_smbus.c"
  37 #include "superio/winbond/w83697hf/early_serial.c"
  38 #include <spd.h>
  39
  40 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
  41 #define DUMMY_DEV PNP_DEV(0x2e, 0)
  42
  43 static const struct mem_controller ctrl = {
  44         .d0f0 = 0x0000,
  45         .d0f2 = 0x2000,
  46         .d0f3 = 0x3000,
  47         .d0f4 = 0x4000,
  48         .d0f7 = 0x7000,
  49         .d1f0 = 0x8000,
  50         .channel0 = { DIMM0 },
  51 };
  52
  53 static inline int spd_read_byte(unsigned device, unsigned address)
  54 {
  55         return smbus_read_byte(device, address);
  56 }
  57
  58 #include "northbridge/via/cn400/raminit.c"
  59
  60 static void enable_mainboard_devices(void)
  61 {
  62         device_t dev;
  63         u8 reg;
  64
  65         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
  66                                 PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
  67         if (dev == PCI_DEV_INVALID)
  68                 die("Southbridge not found!!!\n");
  69
  70         /* bit=0 means enable function (per VT8237R datasheet)
  71          *   7 17.6 MC97
  72          *   6 17.5 AC97
  73          *   5 16.1 USB 2
  74          *   4 16.0 USB 1
  75          *   3 15.0 SATA and PATA
  76          *   2 16.2 USB 3
  77          *   1 16.4 USB EHCI
  78          */
  79         pci_write_config8(dev, 0x50, 0xC0);
  80
  81         /*bit=0 means enable internal function (per VT8237R datasheet)
  82          *   7 USB Device Mode
  83          *bit=1 means enable internal function (per VT8237R datasheet)
  84          *   6 Reserved
  85          *   5 LAN Controller Clock Gating
  86          *   4 LAN Controller
  87          *   3 Internal RTC
  88          *   2 Internal PS2 Mouse
  89          *   1 Internal KBC Configuration
  90          *   0 Internal Keyboard Controller
  91          */
  92         pci_write_config8(dev, 0x51, 0x9d);
  93 }
  94
  95 static void enable_shadow_ram(void)
  96 {
  97         unsigned char shadowreg;
  98
  99         shadowreg = pci_read_config8(ctrl.d0f3, 0x82);
 100         /* 0xf0000-0xfffff Read/Write*/
 101         shadowreg |= 0x30;
 102         pci_write_config8(ctrl.d0f3, 0x82, shadowreg);
 103 }
 104
 105 static void main(unsigned long bist)
 106 {
 107         unsigned long x;
 108         device_t dev;
 109
 110         /* Enable multifunction for northbridge. */
 111         pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 112
 113         w83697hf_set_clksel_48(DUMMY_DEV);
 114         w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 115         console_init();
 116
 117         enable_smbus();
 118         smbus_fixup(&ctrl);
 119
 120         /* Halt if there was a built-in self test failure. */
 121         report_bist_failure(bist);
 122
 123         print_debug("Enabling mainboard devices\n");
 124         enable_mainboard_devices();
 125
 126         print_debug("Enable F-ROM Shadow RAM\n");
 127         enable_shadow_ram();
 128
 129         print_debug("Setup CPU Interface\n");
 130         c3_cpu_setup(ctrl.d0f2);
 131
 132         ddr_ram_setup();
 133
 134         if (bist == 0)
 135                 early_mtrr_init();
 136 }