3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
8 #include <pc80/mc146818rtc.h>
9 #include <console/console.h>
12 #include <cpu/amd/model_fxx_rev.h>
13 #include "northbridge/amd/amdk8/incoherent_ht.c"
14 #include "southbridge/nvidia/ck804/early_smbus.h"
15 #include "northbridge/amd/amdk8/raminit.h"
16 #include "cpu/amd/model_fxx/apic_timer.c"
17 #include "lib/delay.c"
18 #include "cpu/x86/lapic/boot_cpu.c"
19 #include "northbridge/amd/amdk8/reset_test.c"
20 #include "superio/smsc/lpc47b397/early_serial.c"
21 #include "superio/smsc/lpc47b397/early_gpio.c"
22 #include "cpu/x86/bist.h"
23 #include "northbridge/amd/amdk8/debug.c"
24 #include <cpu/amd/mtrr.h>
25 #include "cpu/x86/mtrr/earlymtrr.c"
26 #include "northbridge/amd/amdk8/setup_resource_map.c"
28 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
29 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
30 #define SUPERIO_GPIO_IO_BASE 0x400
32 static void memreset_setup(void) { }
33 static void memreset(int controllers
, const struct mem_controller
*ctrl
) { }
34 static void activate_spd_rom(const struct mem_controller
*ctrl
) { }
36 static void sio_gpio_setup(void)
40 /*Enable onboard scsi*/
41 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE
, 0x2c,
42 (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
43 value
= lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE
, 0x4c);
44 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE
, 0x4c, (value
|(1<<1)));
47 static inline int spd_read_byte(unsigned device
, unsigned address
)
49 return smbus_read_byte(device
, address
);
52 #include "northbridge/amd/amdk8/raminit.c"
53 #include "northbridge/amd/amdk8/coherent_ht.c"
54 #include "lib/generic_sdram.c"
55 #include "resourcemap.c"
56 #include "cpu/amd/dualcore/dualcore.c"
57 #include "southbridge/nvidia/ck804/early_setup_ss.h"
59 //set GPIO to input mode
60 #define CK804_MB_SETUP \
61 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
62 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
63 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
64 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
65 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
66 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
68 #include "southbridge/nvidia/ck804/early_setup_car.c"
69 #include "cpu/amd/car/post_cache_as_ram.c"
70 #include "cpu/amd/model_fxx/init_cpus.c"
71 #include "northbridge/amd/amdk8/early_ht.c"
73 static void sio_setup(void)
79 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE
+1, 0), 0xac, 0x047f0400);
81 byte
= pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE
+1 , 0), 0x7b);
83 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE
+1 , 0), 0x7b, byte
);
85 dword
= pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE
+1 , 0), 0xa0);
86 dword
|= (1<<29)|(1<<0);
87 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE
+1 , 0), 0xa0, dword
);
89 dword
= pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE
+1, 0), 0xa4);
91 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE
+1 , 0), 0xa4, dword
);
93 lpc47b397_enable_serial(SUPERIO_GPIO_DEV
, SUPERIO_GPIO_IO_BASE
);
94 value
= lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE
, 0x77);
96 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE
, 0x77, value
);
99 void cache_as_ram_main(unsigned long bist
, unsigned long cpu_init_detectedx
)
101 static const u16 spd_addr
[] = {
109 unsigned bsp_apicid
= 0, nodes
;
110 struct mem_controller ctrl
[8];
112 if (!cpu_init_detectedx
&& boot_cpu()) {
113 /* Nothing special needs to be done to find bus 0 */
114 /* Allow the HT devices to be found */
115 enumerate_ht_chain();
120 bsp_apicid
= init_cpus(cpu_init_detectedx
);
122 lpc47b397_enable_serial(SERIAL_DEV
, CONFIG_TTYS0_BASE
);
125 /* Halt if there was a built in self test failure */
126 report_bist_failure(bist
);
130 setup_mb_resource_map();
132 needs_reset
= setup_coherent_ht_domain();
134 wait_all_core0_started();
136 // It is said that we should start core1 after all core0 launched
138 wait_all_other_cores_started(bsp_apicid
);
140 needs_reset
|= ht_setup_chains_x();
141 needs_reset
|= ck804_early_setup_x();
143 printk(BIOS_INFO
, "ht reset -\n");
147 allow_all_aps_stop(bsp_apicid
);
150 //It's the time to set ctrl now;
151 fill_mem_ctrl(nodes
, ctrl
, spd_addr
);
156 sdram_initialize(nodes
, ctrl
);