src/mainboard/gigabyte/ma78gm/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 //#define SYSTEM_TYPE 0 /* SERVER */
  21 #define SYSTEM_TYPE 1   /* DESKTOP */
  22 //#define SYSTEM_TYPE 2 /* MOBILE */
  23
  24 //used by incoherent_ht
  25 #define FAM10_SCAN_PCI_BUS 0
  26 #define FAM10_ALLOCATE_IO_RANGE 0
  27
  28 #include <stdint.h>
  29 #include <string.h>
  30 #include <device/pci_def.h>
  31 #include <device/pci_ids.h>
  32 #include <arch/io.h>
  33 #include <device/pnp_def.h>
  34 #include <arch/romcc_io.h>
  35 #include <cpu/x86/lapic.h>
  36 #include <console/console.h>
  37 #include <cpu/amd/model_10xxx_rev.h>
  38 #include "northbridge/amd/amdfam10/raminit.h"
  39 #include "northbridge/amd/amdfam10/amdfam10.h"
  40 #include <lib.h>
  41 #include "cpu/x86/lapic/boot_cpu.c"
  42 #include "northbridge/amd/amdfam10/reset_test.c"
  43 #include <console/loglevel.h>
  44 #include "cpu/x86/bist.h"
  45 #include "superio/ite/it8718f/early_serial.c"
  46 #include <usbdebug.h>
  47 #include "cpu/x86/mtrr/earlymtrr.c"
  48 #include <cpu/amd/mtrr.h>
  49 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  50 #include "southbridge/amd/rs780/early_setup.c"
  51 #include "southbridge/amd/sb700/early_setup.c"
  52 #include "northbridge/amd/amdfam10/debug.c"
  53
  54 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  55
  56 static int spd_read_byte(u32 device, u32 address)
  57 {
  58         return smbus_read_byte(device, address);
  59 }
  60
  61 #include "northbridge/amd/amdfam10/amdfam10.h"
  62 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
  63 #include "northbridge/amd/amdfam10/pci.c"
  64 #include "resourcemap.c"
  65 #include "cpu/amd/quadcore/quadcore.c"
  66 #include "cpu/amd/car/post_cache_as_ram.c"
  67 #include "cpu/amd/microcode/microcode.c"
  68
  69 #if CONFIG_UPDATE_CPU_MICROCODE
  70 #include "cpu/amd/model_10xxx/update_microcode.c"
  71 #endif
  72
  73 #include "cpu/amd/model_10xxx/init_cpus.c"
  74 #include "northbridge/amd/amdfam10/early_ht.c"
  75 #include <spd.h>
  76
  77 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  78 {
  79         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  80         static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
  81         u32 bsp_apicid = 0, val;
  82         msr_t msr;
  83
  84         if (!cpu_init_detectedx && boot_cpu()) {
  85                 /* Nothing special needs to be done to find bus 0 */
  86                 /* Allow the HT devices to be found */
  87                 /* mov bsp to bus 0xff when > 8 nodes */
  88                 set_bsp_node_CHtExtNodeCfgEn();
  89                 enumerate_ht_chain();
  90                 sb7xx_51xx_pci_port80();
  91         }
  92
  93         post_code(0x30);
  94
  95         if (bist == 0) {
  96                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
  97                 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
  98         }
  99
 100         post_code(0x32);
 101
 102         enable_rs780_dev8();
 103         sb7xx_51xx_lpc_init();
 104
 105         it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 106         it8718f_disable_reboot();
 107
 108         console_init();
 109
 110         /* Halt if there was a built in self test failure */
 111         report_bist_failure(bist);
 112
 113         // Load MPB
 114         val = cpuid_eax(1);
 115         printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 116         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 117         printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
 118         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 119
 120         /* Setup sysinfo defaults */
 121         set_sysinfo_in_ram(0);
 122
 123 #if CONFIG_UPDATE_CPU_MICROCODE
 124         update_microcode(val);
 125 #endif
 126         post_code(0x33);
 127
 128         cpuSetAMDMSR();
 129         post_code(0x34);
 130
 131         amd_ht_init(sysinfo);
 132         post_code(0x35);
 133
 134         /* Setup nodes PCI space and start core 0 AP init. */
 135         finalize_node_setup(sysinfo);
 136
 137         /* Setup any mainboard PCI settings etc. */
 138         setup_mb_resource_map();
 139         post_code(0x36);
 140
 141         /* wait for all the APs core0 started by finalize_node_setup. */
 142         /* FIXME: A bunch of cores are going to start output to serial at once.
 143            It would be nice to fixup prink spinlocks for ROM XIP mode.
 144            I think it could be done by putting the spinlock flag in the cache
 145            of the BSP located right after sysinfo.
 146          */
 147         wait_all_core0_started();
 148
 149 #if CONFIG_LOGICAL_CPUS==1
 150         /* Core0 on each node is configured. Now setup any additional cores. */
 151         printk(BIOS_DEBUG, "start_other_cores()\n");
 152         start_other_cores();
 153         post_code(0x37);
 154         wait_all_other_cores_started(bsp_apicid);
 155 #endif
 156
 157         post_code(0x38);
 158
 159         /* run _early_setup before soft-reset. */
 160         rs780_early_setup();
 161         sb7xx_51xx_early_setup();
 162
 163 #if CONFIG_SET_FIDVID
 164         msr = rdmsr(0xc0010071);
 165         printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 166
 167         /* FIXME: The sb fid change may survive the warm reset and only
 168            need to be done once.*/
 169         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 170
 171         post_code(0x39);
 172
 173         if (!warm_reset_detect(0)) {                    // BSP is node 0
 174                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 175         } else {
 176                 init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0
 177         }
 178
 179         post_code(0x3A);
 180
 181         /* show final fid and vid */
 182         msr=rdmsr(0xc0010071);
 183         printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 184 #endif
 185
 186         rs780_htinit();
 187
 188         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 189         if (!warm_reset_detect(0)) {
 190                 print_info("...WARM RESET...\n\n\n");
 191                 soft_reset();
 192                 die("After soft_reset_x - shouldn't see this message!!!\n");
 193         }
 194
 195         post_code(0x3B);
 196
 197         /* It's the time to set ctrl in sysinfo now; */
 198         printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 199         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 200
 201         post_code(0x40);
 202
 203 //      die("Die Before MCT init.");
 204
 205         printk(BIOS_DEBUG, "raminit_amdmct()\n");
 206         raminit_amdmct(sysinfo);
 207         post_code(0x41);
 208
 209 /*
 210         dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
 211         dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
 212         dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
 213         dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 214 */
 215
 216 //      die("After MCT init before CAR disabled.");
 217
 218         rs780_before_pci_init();
 219         sb7xx_51xx_before_pci_init();
 220
 221         post_code(0x42);
 222         printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 223         post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
 224         post_code(0x43);        // Should never see this post code.
 225 }
 226
 227 /**
 228  * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
 229  * Description:
 230  *      This routine is called every time a non-coherent chain is processed.
 231  *      BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
 232  *      swap list. The first part of the list controls the BUID assignment and the
 233  *      second part of the list provides the device to device linking.  Device orientation
 234  *      can be detected automatically, or explicitly.  See documentation for more details.
 235  *
 236  *      Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 237  *      based on each device's unit count.
 238  *
 239  * Parameters:
 240  *      @param[in]  u8  node    = The node on which this chain is located
 241  *      @param[in]  u8  link    = The link on the host for this chain
 242  *      @param[out] u8** list   = supply a pointer to a list
 243  *      @param[out] BOOL result = true to use a manual list
 244  *                                false to initialize the link automatically
 245  */
 246 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 247 {
 248         static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 249         /* If the BUID was adjusted in early_ht we need to do the manual override */
 250         if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
 251                 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 252                 if ((node == 0) && (link == 0)) {       /* BSP SB link */
 253                         *List = swaplist;
 254                         return 1;
 255                 }
 256         }
 257
 258         return 0;
 259 }