2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2006 MSI
7 * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
8 * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 unsigned int get_sbdn(unsigned bus
);
27 #if CONFIG_K8_REV_F_SUPPORT == 1
28 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
33 #include <device/pci_def.h>
35 #include <device/pnp_def.h>
36 #include <arch/romcc_io.h>
37 #include <cpu/amd/mtrr.h>
38 #include <cpu/x86/lapic.h>
39 #include <pc80/mc146818rtc.h>
40 #include <console/console.h>
41 #include <cpu/amd/model_fxx_rev.h>
42 #include "northbridge/amd/amdk8/raminit.h"
43 #include "cpu/amd/model_fxx/apic_timer.c"
44 #include "lib/delay.c"
45 #include "northbridge/amd/amdk8/reset_test.c"
46 #include "northbridge/amd/amdk8/debug.c"
47 #include "superio/ite/it8712f/early_serial.c"
48 #include "southbridge/via/vt8237r/early_smbus.c"
49 #include "cpu/x86/mtrr/earlymtrr.c"
50 #include "cpu/x86/bist.h"
51 #include "northbridge/amd/amdk8/setup_resource_map.c"
54 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
55 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
57 static void memreset(int controllers
, const struct mem_controller
*ctrl
) { }
58 static void activate_spd_rom(const struct mem_controller
*ctrl
) { }
60 static inline int spd_read_byte(unsigned device
, unsigned address
)
62 return smbus_read_byte(device
, address
);
65 #include "southbridge/via/k8t890/early_car.c"
66 #include "northbridge/amd/amdk8/amdk8.h"
67 #include "northbridge/amd/amdk8/incoherent_ht.c"
68 #include "northbridge/amd/amdk8/coherent_ht.c"
69 #include "northbridge/amd/amdk8/raminit_f.c"
70 #include "lib/generic_sdram.c"
71 #include "cpu/amd/dualcore/dualcore.c"
72 #include "cpu/amd/car/post_cache_as_ram.c"
73 #include "cpu/amd/model_fxx/init_cpus.c"
77 /* this function might fail on some K8 CPUs with errata #181 */
78 static void ldtstop_sb(void)
80 print_debug("toggle LDTSTP#\n");
81 u8 reg
= inb (VT8237R_ACPI_IO_BASE
+ 0x5c);
83 outb(reg
, VT8237R_ACPI_IO_BASE
+ 0x5c);
84 reg
= inb(VT8237R_ACPI_IO_BASE
+ 0x15);
85 print_debug("done\n");
88 #include "cpu/amd/model_fxx/fidvid.c"
89 #include "northbridge/amd/amdk8/resourcemap.c"
96 print_debug("soft reset \n");
99 tmp
= pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
101 /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
102 pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp
);
105 /* daisy daisy ... */
110 unsigned int get_sbdn(unsigned bus
)
114 dev
= pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA
,
115 PCI_DEVICE_ID_VIA_VT8237R_LPC
), bus
);
116 return (dev
>> 15) & 0x1f;
119 void cache_as_ram_main(unsigned long bist
, unsigned long cpu_init_detectedx
)
121 static const uint16_t spd_addr
[] = {
129 unsigned bsp_apicid
= 0;
131 struct sys_info
*sysinfo
=
132 (struct sys_info
*)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE
- CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
);
134 it8712f_enable_serial(SERIAL_DEV
, CONFIG_TTYS0_BASE
);
135 it8712f_kill_watchdog();
136 it8712f_enable_3vsbsw();
140 printk(BIOS_INFO
, "now booting... \n");
143 bsp_apicid
= init_cpus(cpu_init_detectedx
, sysinfo
);
145 /* Halt if there was a built in self test failure. */
146 report_bist_failure(bist
);
147 setup_default_resource_map();
148 setup_coherent_ht_domain();
149 wait_all_core0_started();
151 printk(BIOS_INFO
, "now booting... All core 0 started\n");
153 #if CONFIG_LOGICAL_CPUS==1
154 /* It is said that we should start core1 after all core0 launched. */
156 wait_all_other_cores_started(bsp_apicid
);
159 ht_setup_chains_x(sysinfo
); /* Init sblnk and sbbusn, nodes, sbdn. */
161 needs_reset
= optimize_link_coherent_ht();
162 print_debug_hex8(needs_reset
);
163 needs_reset
|= optimize_link_incoherent_ht(sysinfo
);
164 print_debug_hex8(needs_reset
);
165 needs_reset
|= k8t890_early_setup_ht();
166 print_debug_hex8(needs_reset
);
168 vt8237_early_network_init(NULL
);
169 vt8237_early_spi_init();
172 printk(BIOS_DEBUG
, "ht reset -\n");
174 printk(BIOS_DEBUG
, "FAILED!\n");
177 /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
178 /* allow LDT STOP asserts */
179 vt8237_sb_enable_fid_vid();
182 print_debug("after enable_fid_change\n");
184 init_fidvid_bsp(bsp_apicid
);
186 /* Stop the APs so we can start them later in init. */
187 allow_all_aps_stop(bsp_apicid
);
189 /* It's the time to set ctrl now. */
190 fill_mem_ctrl(sysinfo
->nodes
, sysinfo
->ctrl
, spd_addr
);
192 sdram_initialize(sysinfo
->nodes
, sysinfo
->ctrl
, sysinfo
);