src/mainboard/aopen/dxplplusu/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stdint.h>
  17 #include <device/pci_def.h>
  18 #include <arch/io.h>
  19 #include <arch/cpu.h>
  20 #include <stdlib.h>
  21 #include <console/console.h>
  22 #include <cpu/x86/bist.h>
  23 #include <cpu/intel/romstage.h>
  24
  25 #include <southbridge/intel/i82801dx/i82801dx.h>
  26 #include <northbridge/intel/e7505/raminit.h>
  27
  28 #include <device/pnp_def.h>
  29 #include <superio/smsc/lpc47m10x/lpc47m10x.h>
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1)
  32
  33 int spd_read_byte(unsigned device, unsigned address)
  34 {
  35         return smbus_read_byte(device, address);
  36 }
  37
  38 void mainboard_romstage_entry(unsigned long bist)
  39 {
  40         static const struct mem_controller memctrl[] = {
  41                 {
  42                         .d0 = PCI_DEV(0, 0, 0),
  43                         .d0f1 = PCI_DEV(0, 0, 1),
  44                         .channel0 = { 0x50, 0x52, 0, 0 },
  45                         .channel1 = { 0x51, 0x53, 0, 0 },
  46                 },
  47         };
  48
  49         // Get the serial port running and print a welcome banner
  50         lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  51         console_init();
  52
  53         // Halt if there was a built in self test failure
  54         report_bist_failure(bist);
  55
  56         // If this is a warm boot, some initialization can be skipped
  57         if (!e7505_mch_is_ready()) {
  58                 enable_smbus();
  59
  60                 /* The real MCH initialisation. */
  61                 e7505_mch_init(memctrl);
  62
  63                 /*
  64                  * ECC scrub invalidates cache, so all stack in CAR
  65                  * is lost. Only return addresses from main() and
  66                  * scrub_ecc() are recovered to stack via xmm0-xmm3.
  67                  */
  68 #if CONFIG_HW_SCRUBBER
  69 #if !CONFIG_USBDEBUG_IN_ROMSTAGE
  70                 unsigned long ret_addr = (unsigned long)((unsigned long*)&bist - 1);
  71                 e7505_mch_scrub_ecc(ret_addr);
  72 #endif
  73 #endif
  74
  75                 /* Hook for post ECC scrub settings and debug. */
  76                 e7505_mch_done(memctrl);
  77         }
  78
  79         printk(BIOS_DEBUG, "SDRAM is up.\n");
  80 }