3 config NO_BOOTBLOCK_CONSOLE
6 config BOOTBLOCK_CONSOLE
7 bool "Enable early (bootblock) console output."
8 depends on !NO_BOOTBLOCK_CONSOLE
11 Use console during the bootblock if supported
13 config POSTCAR_CONSOLE
14 bool "Enable console output during postcar."
15 depends on POSTCAR_STAGE
18 Use console during the postcar if supported
20 config SQUELCH_EARLY_SMP
21 bool "Squelch AP CPUs from early console."
25 When selected only the BSP CPU will output to early console.
27 Console drivers have unpredictable behaviour if multiple threads
28 attempt to share the same resources without a spinlock.
33 bool "Serial port console output"
35 depends on DRIVERS_UART
37 Send coreboot debug output to a serial port.
39 The type of serial port driver selected based on your configuration is
40 shown on the following menu line. Supporting multiple different types
41 of UARTs in one build is not supported.
43 config FIXED_UART_FOR_CONSOLE
46 Select to remove the prompt from UART_FOR_CONSOLE in case a
47 specific UART has to be used (e.g. when the platform code
48 performs dangerous configurations).
52 comment "I/O mapped, 8250-compatible"
53 depends on DRIVERS_UART_8250IO
55 comment "memory mapped, 8250-compatible"
56 depends on DRIVERS_UART_8250MEM
58 comment "device-specific UART"
59 depends on HAVE_UART_SPECIAL
61 config UART_FOR_CONSOLE
63 prompt "Index for UART port to use for console" if !FIXED_UART_FOR_CONSOLE
66 Select an I/O port to use for serial console:
67 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8
69 # FIXME: Early programming in romstage is incorrect as we should
70 # program different LDN to actually change the physical port.
73 depends on DRIVERS_UART
74 default 0x3f8 if UART_FOR_CONSOLE = 0
75 default 0x2f8 if UART_FOR_CONSOLE = 1
76 default 0x3e8 if UART_FOR_CONSOLE = 2
77 default 0x2e8 if UART_FOR_CONSOLE = 3
79 Map the COM port number to the respective I/O port.
81 comment "Serial port base address = 0x3f8"
82 depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 0
83 comment "Serial port base address = 0x2f8"
84 depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 1
85 comment "Serial port base address = 0x3e8"
86 depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 2
87 comment "Serial port base address = 0x2e8"
88 depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 3
90 config UART_OVERRIDE_BAUDRATE
93 Set to "y" when the platform overrides the baudrate by providing
94 a get_uart_baudrate routine.
96 if !UART_OVERRIDE_BAUDRATE
100 default CONSOLE_SERIAL_115200
102 config CONSOLE_SERIAL_921600
105 Set serial port Baud rate to 921600.
106 config CONSOLE_SERIAL_460800
109 Set serial port Baud rate to 460800.
110 config CONSOLE_SERIAL_230400
113 Set serial port Baud rate to 230400.
114 config CONSOLE_SERIAL_115200
117 Set serial port Baud rate to 115200.
118 config CONSOLE_SERIAL_57600
121 Set serial port Baud rate to 57600.
122 config CONSOLE_SERIAL_38400
125 Set serial port Baud rate to 38400.
126 config CONSOLE_SERIAL_19200
129 Set serial port Baud rate to 19200.
130 config CONSOLE_SERIAL_9600
133 Set serial port Baud rate to 9600.
137 #FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!)
140 default 921600 if CONSOLE_SERIAL_921600
141 default 460800 if CONSOLE_SERIAL_460800
142 default 230400 if CONSOLE_SERIAL_230400
143 default 115200 if CONSOLE_SERIAL_115200
144 default 57600 if CONSOLE_SERIAL_57600
145 default 38400 if CONSOLE_SERIAL_38400
146 default 19200 if CONSOLE_SERIAL_19200
147 default 9600 if CONSOLE_SERIAL_9600
149 Map the Baud rates to an integer.
153 # TODO: Allow user-friendly selection of settings other than 8n1.
157 depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM
159 endif # CONSOLE_SERIAL
162 bool "spkmodem (console on speaker) console output"
166 Send coreboot debug output through speaker
169 bool "USB dongle console output"
173 Send coreboot debug output to USB.
175 Configuration for USB hardware is under menu Generic Drivers.
178 # TODO: Improve description.
180 bool "Network console over NE2000 compatible Ethernet adapter"
184 Send coreboot debug output to a Ethernet console, it works
185 same way as Linux netconsole, packets are received to UDP
186 port 6666 on IP/MAC specified with options bellow.
187 Use following netcat command: nc -u -l -p 6666
189 config CONSOLE_NE2K_DST_MAC
190 depends on CONSOLE_NE2K
191 string "Destination MAC address of remote system"
192 default "00:13:d4:76:a2:ac"
194 Type in either MAC address of logging system or MAC address
197 config CONSOLE_NE2K_DST_IP
198 depends on CONSOLE_NE2K
199 string "Destination IP of logging system"
202 This is IP address of the system running for example
203 netcat command to dump the packets.
205 config CONSOLE_NE2K_SRC_IP
206 depends on CONSOLE_NE2K
207 string "IP address of coreboot system"
210 This is the IP of the coreboot system
212 config CONSOLE_NE2K_IO_PORT
213 depends on CONSOLE_NE2K
214 hex "NE2000 adapter fixed IO port address"
217 This is the IO port address for the IO port
218 on the card, please select some non-conflicting region,
219 32 bytes of IO spaces will be used (and align on 32 bytes
220 boundary, qemu needs broader align)
223 bool "Send console output to a CBMEM buffer"
226 Enable this to save the console output in a CBMEM buffer. This would
227 allow to see coreboot console output from Linux space.
231 config CONSOLE_CBMEM_BUFFER_SIZE
232 hex "Room allocated for console output in CBMEM"
235 Space allocated for console output storage in CBMEM. The default
236 value (128K or 0x20000 bytes) is large enough to accommodate
237 even the BIOS_SPEW level.
239 config CONSOLE_CBMEM_DUMP_TO_UART
240 depends on !CONSOLE_SERIAL
241 bool "Dump CBMEM console on resets"
244 Enable this to have CBMEM console buffer contents dumped on the
245 serial output in case serial console is disabled and the device
246 resets itself while trying to boot the payload.
250 config CONSOLE_SPI_FLASH
251 bool "SPI Flash console output"
253 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if !COMMON_CBFS_SPI_WRAPPER
255 Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area
257 This option can cause premature wear on the SPI flash and should not
258 be used as a normal means of debugging. It is only to be enabled and
259 used when porting a new motherboard which has no other console
260 available (no UART, no POST, no cbmem access(non bootable)). Since
261 a non bootable machine will require the use of an external SPI Flash
262 programmer, the developer can grab the console log at the same time.
264 The flash console will not be erased on reboot, so once it is full,
265 the flashconsole driver will stop writing to it. This is to avoid
266 wear on the flash, and to avoid erasing sectors (which may freeze
267 the SPI controller on skylake).
269 The 'CONSOLE' area can be extracted from the FMAP with :
270 cbfstool rom.bin read -r CONSOLE -f console.log
272 config CONSOLE_SPI_FLASH_BUFFER_SIZE
273 hex "Room allocated for console output in FMAP"
275 depends on CONSOLE_SPI_FLASH
277 Space allocated for console output storage in FMAP. The default
278 value (128K or 0x20000 bytes) is large enough to accommodate
279 even the BIOS_SPEW level.
281 config CONSOLE_QEMU_DEBUGCON
282 bool "QEMU debug console output"
283 depends on CPU_QEMU_X86
286 Send coreboot debug output to QEMU's isa-debugcon device:
289 -chardev file,id=debugcon,path=/dir/file.log \
290 -device isa-debugcon,iobase=0x402,chardev=debugcon
292 config CONSOLE_QEMU_DEBUGCON_PORT
293 hex "QEMU debug console port"
294 depends on CONSOLE_QEMU_DEBUGCON
298 bool "SPI debug console output"
299 depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH
301 Enable support for the debug console on the Dediprog EM100Pro.
302 This is currently working only in ramstage due to how the spi
305 config CONSOLE_OVERRIDE_LOGLEVEL
308 Set to "y" when the platform overrides the loglevel by providing
309 a get_console_loglevel routine.
311 if !CONSOLE_OVERRIDE_LOGLEVEL
314 prompt "Default console log level"
315 default DEFAULT_CONSOLE_LOGLEVEL_8 if CHROMEOS
316 default DEFAULT_CONSOLE_LOGLEVEL_7
318 config DEFAULT_CONSOLE_LOGLEVEL_8
321 Way too many details.
322 config DEFAULT_CONSOLE_LOGLEVEL_7
325 Debug-level messages.
326 config DEFAULT_CONSOLE_LOGLEVEL_6
329 Informational messages.
330 config DEFAULT_CONSOLE_LOGLEVEL_5
333 Normal but significant conditions.
334 config DEFAULT_CONSOLE_LOGLEVEL_4
338 config DEFAULT_CONSOLE_LOGLEVEL_3
342 config DEFAULT_CONSOLE_LOGLEVEL_2
346 config DEFAULT_CONSOLE_LOGLEVEL_1
349 Action must be taken immediately.
350 config DEFAULT_CONSOLE_LOGLEVEL_0
357 config DEFAULT_CONSOLE_LOGLEVEL
359 default 0 if DEFAULT_CONSOLE_LOGLEVEL_0
360 default 1 if DEFAULT_CONSOLE_LOGLEVEL_1
361 default 2 if DEFAULT_CONSOLE_LOGLEVEL_2
362 default 3 if DEFAULT_CONSOLE_LOGLEVEL_3
363 default 4 if DEFAULT_CONSOLE_LOGLEVEL_4
364 default 5 if DEFAULT_CONSOLE_LOGLEVEL_5
365 default 6 if DEFAULT_CONSOLE_LOGLEVEL_6
366 default 7 if DEFAULT_CONSOLE_LOGLEVEL_7
367 default 8 if DEFAULT_CONSOLE_LOGLEVEL_8
369 Map the log level config names to an integer.
374 bool "Don't show any POST codes"
378 bool "Store post codes in CMOS for debugging"
379 depends on !NO_POST && PC80_SYSTEM
382 If enabled, coreboot will store post codes in CMOS and switch between
383 two offsets on each boot so the last post code in the previous boot
384 can be retrieved. This uses 3 bytes of CMOS.
386 config CMOS_POST_OFFSET
387 hex "Offset into CMOS to store POST codes"
391 If CMOS_POST is enabled then an offset into CMOS must be provided.
392 If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
393 defined in the mainboard option table.
396 bool "Show POST codes on the debug console"
400 If enabled, coreboot will additionally print POST codes (which are
401 usually displayed using a so-called "POST card" ISA/PCI/PCI-E
402 device) on the debug console.
405 bool "Send POST codes to an external device"
410 prompt "Device to send POST codes to"
411 depends on POST_DEVICE
412 default POST_DEVICE_LPC if DEFAULT_POST_ON_LPC
413 default POST_DEVICE_NONE
415 config POST_DEVICE_NONE
417 config POST_DEVICE_LPC
420 config POST_DEVICE_PCI_PCIE
425 config DEFAULT_POST_ON_LPC
430 bool "Send POST codes to an IO port"
431 depends on PC80_SYSTEM && !NO_POST
434 If enabled, POST codes will be written to an IO port.
438 hex "IO port for POST codes"
441 POST codes on x86 are typically written to the LPC bus on port
442 0x80. However, it may be desirable to change the port number
443 depending on the presence of coprocessors/microcontrollers or if the
444 platform does not support IO in the conventional x86 manner.
446 config NO_EARLY_BOOTBLOCK_POSTCODES
449 Some chipsets require that the routing for the port 80h POST
450 code be configured before any POST codes are sent out.
451 This can be done in the boot block, but there are a couple of
452 POST codes that go out before the chipset's bootblock initialization
453 can happen. This option suppresses those POST codes.
455 config HWBASE_DEBUG_CB
457 default y if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
460 config HWBASE_DEBUG_NULL
462 depends on !HWBASE_DEBUG_CB