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cpu/amd: Use common AMD's MSR
[coreboot.git] / src / southbridge / amd / rs780 / early_setup.c
blob865b577279afbd45dd820f49f833f9cd7b30b0d4
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <types.h>
17 #include <arch/io.h>
18 #include <northbridge/amd/amdmct/mct/mct_d.h>
19 #include <console/console.h>
20 #include <cpu/x86/msr.h>
21 #include <cpu/amd/msr.h>
22
23 #include "rev.h"
24 #include "rs780.h"
25
26 #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
27 #define NBMISC_INDEX 0x60
28 #define NBMC_INDEX 0xE8
29
30 static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
31 {
32 pci_write_config32(dev, index_reg, index);
33 return pci_read_config32(dev, index_reg + 0x4);
34 }
35
36 static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data)
37 {
38 pci_write_config32(dev, index_reg, index /* | 0x80 */ );
39 pci_write_config32(dev, index_reg + 0x4, data);
40 }
41
42 static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
43 {
44 return nb_read_index((nb_dev), NBMISC_INDEX, (index));
45 }
46
47 static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
48 {
49 nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
50 }
51
52 static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
53 {
54 return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
55 }
56
57 static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
58 {
59 nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
60 }
61
62 static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
63 {
64 return nb_read_index((nb_dev), NBMC_INDEX, (index));
65 }
66
67 static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
68 {
69 nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
70 }
71
72 static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
73 u32 val)
74 {
75 u32 reg_old, reg;
76 reg = reg_old = htiu_read_index(nb_dev, reg_pos);
77 reg &= ~mask;
78 reg |= val;
79 if (reg != reg_old) {
80 htiu_write_index(nb_dev, reg_pos, reg);
81 }
82 }
83
84 static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
85 u32 val)
86 {
87 u32 reg_old, reg;
88 reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
89 reg &= ~mask;
90 reg |= val;
91 if (reg != reg_old) {
92 nbmisc_write_index(nb_dev, reg_pos, reg);
93 }
94 }
95
96 static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
97 u32 val)
98 {
99 u32 reg_old, reg;
100 reg = reg_old = pci_read_config32(nb_dev, reg_pos);
101 reg &= ~mask;
102 reg |= val;
103 if (reg != reg_old) {
104 pci_write_config32(nb_dev, reg_pos, reg);
105 }
106 }
107 /* family 10 only, for reg > 0xFF */
108 #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
109 static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos,
110 u32 mask, u32 val)
111 {
112 u32 reg_old, reg;
113 reg = reg_old = Get_NB32(fam10_dev, reg_pos);
114 reg &= ~mask;
115 reg |= val;
116 if (reg != reg_old) {
117 Set_NB32(fam10_dev, reg_pos, reg);
118 }
119 }
120 #else
121 #define set_fam10_ext_cfg_enable_bits(a, b, c, d) do {} while (0)
122 #endif
123
124
125 static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,
126 u8 val)
127 {
128 u8 reg_old, reg;
129 reg = reg_old = pci_read_config8(nb_dev, reg_pos);
130 reg &= ~mask;
131 reg |= val;
132 if (reg != reg_old) {
133 pci_write_config8(nb_dev, reg_pos, reg);
134 }
135 }
136
137 static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
138 u32 val)
139 {
140 u32 reg_old, reg;
141 reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
142 reg &= ~mask;
143 reg |= val;
144 if (reg != reg_old) {
145 nbmc_write_index(nb_dev, reg_pos, reg);
146 }
147 }
148
149 static u8 is_famly10(void)
150 {
151 return (cpuid_eax(1) & 0xff00000) != 0;
152 }
153
154 #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
155 static u8 l3_cache(void)
156 {
157 return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
158 }
159
160 static u8 cpu_core_number(void)
161 {
162 return (cpuid_ecx(0x80000008) & 0xFF) + 1;
163 }
164 #endif
165
166 /*****************************************
167 * Init HT link speed/width for rs780 -- k8 link
168 * 1: Check CPU Family, Family10?
169 * 2: Get CPU's HT speed and width
170 * 3: Decide HT mode 1 or 3 by HT Speed. >1GHz: HT3, else HT1
171 *****************************************/
172 static const u8 rs780_ibias[] = {
173 /* 1, 3 are reserved. */
174 [0x0] = 0x4C, /* 200MHz HyperTransport 1 only */
175 [0x2] = 0x4C, /* 400MHz HyperTransport 1 only */
176 [0x4] = 0xB6, /* 600MHz HyperTransport 1 only */
177 [0x5] = 0x4C, /* 800MHz HyperTransport 1 only */
178 [0x6] = 0x9D, /* 1GHz HyperTransport 1 only */
179 /* HT3 for Family 10 */
180 [0x7] = 0xB6, /* 1.2GHz HyperTransport 3 only */
181 [0x8] = 0x2B, /* 1.4GHz HyperTransport 3 only */
182 [0x9] = 0x4C, /* 1.6GHz HyperTransport 3 only */
183 [0xa] = 0x6C, /* 1.8GHz HyperTransport 3 only */
184 [0xb] = 0x9D, /* 2.0GHz HyperTransport 3 only */
185 [0xc] = 0xAD, /* 2.2GHz HyperTransport 3 only */
186 [0xd] = 0xB6, /* 2.4GHz HyperTransport 3 only */
187 [0xe] = 0xC6, /* 2.6GHz HyperTransport 3 only */
188 };
189
190 void rs780_htinit(void)
191 {
192 /*
193 * About HT, it has been done in enumerate_ht_chain().
194 */
195 pci_devfn_t cpu_f0, rs780_f0, clk_f1;
196 u32 reg;
197 u8 cpu_ht_freq, ibias;
198
199 cpu_f0 = PCI_DEV(0, 0x18, 0);
200 /************************
201 * get cpu's ht freq, in cpu's function 0, offset 0x88
202 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
203 * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
204 * value to this reg, and that value takes effect on the next warm reset or
205 * LDTSTOP_L disconnect sequence.
206 * please see the table rs780_ibias about the value and its corresponding frequency.
207 ************************/
208 reg = pci_read_config32(cpu_f0, 0x88);
209 cpu_ht_freq = (reg & 0xf00) >> 8;
210 printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq);
211 rs780_f0 = PCI_DEV(0, 0, 0);
212 //set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28);
213
214 clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */
215
216 ibias = rs780_ibias[cpu_ht_freq];
217
218 /* If HT freq>1GHz, we assume the CPU is fam10, else it is K8.
219 * Is it appropriate?
220 * Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases.
221 * So we check 6 only, it would be faster. */
222 if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) ||
223 (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) {
224 printk(BIOS_INFO, "rs780_htinit: HT1 mode\n");
225
226 /* HT1 mode, RPR 8.4.2 */
227 /* set IBIAS code */
228 set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
229 /* Optimizes chipset HT transmitter drive strength */
230 set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
231 } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
232 printk(BIOS_INFO, "rs780_htinit: HT3 mode\n");
233
234 #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
235 /* HT3 mode, RPR 8.4.3 */
236 set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);
237
238 /* set IBIAS code */
239 set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
240 /* Optimizes chipset HT transmitter drive strength */
241 set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
242 /* Enables error-retry mode */
243 set_nbcfg_enable_bits(rs780_f0, 0x44, 0x1, 0x1);
244 /* Enables scrambling and Disables command throttling */
245 set_nbcfg_enable_bits(rs780_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14));
246 /* Enables transmitter de-emphasis */
247 set_nbcfg_enable_bits(rs780_f0, 0xa4, 1 << 31, 1 << 31);
248 /* Enables transmitter de-emphasis level */
249 /* Sets training 0 time */
250 set_nbcfg_enable_bits(rs780_f0, 0xa0, 0x3F, 0x14);
251
252 /* Enables strict TM4 detection */
253 set_htiu_enable_bits(rs780_f0, 0x15, 0x1 << 22, 0x1 << 22);
254 /* Enables proper DLL reset sequence */
255 set_htiu_enable_bits(rs780_f0, 0x16, 0x1 << 10, 0x1 << 10);
256
257 /* HyperTransport 3 Processor register settings to be done in northbridge */
258 /* Enables error-retry mode */
259 set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130, 1 << 0, 1 << 0);
260 /* Enables scrambling */
261 set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170, 1 << 3, 1 << 3);
262 /* Enables transmitter de-emphasis
263 * This depends on the PCB design and the trace */
264 /* TODO: */
265 /* Disables command throttling */
266 set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10);
267 /* Sets Training 0 Time. See T0Time table for encodings */
268 set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20);
269 /* TODO: */
270 #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
271 }
272 }
273
274 #if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
275 /*******************************************************
276 * Optimize k8 with UMA.
277 * See BKDG_NPT_0F guide for details.
278 * The processor node is addressed by its Node ID on the HT link and can be
279 * accessed with a device number in the PCI configuration space on Bus0.
280 * The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
281 * to Device 25, and so on.
282 * The processor implements configuration registers in PCI configuration
283 * space using the following four headers
284 * Function0: HT technology configuration
285 * Function1: Address map configuration
286 * Function2: DRAM and HT technology Trace mode configuration
287 * Function3: Miscellaneous configuration
288 *******************************************************/
289 static void k8_optimization(void)
290 {
291 pci_devfn_t k8_f0, k8_f2, k8_f3;
292 msr_t msr;
293
294 printk(BIOS_INFO, "k8_optimization()\n");
295 k8_f0 = PCI_DEV(0, 0x18, 0);
296 k8_f2 = PCI_DEV(0, 0x18, 2);
297 k8_f3 = PCI_DEV(0, 0x18, 3);
298
299 /* 8.6.6 K8 Buffer Allocation Settings */
300 pci_write_config32(k8_f0, 0x90, 0x01700169); /* CIM NPT_Optimization */
301 set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
302 set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 26, 3 << 26);
303 set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
304 /* set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); */ /* TODO */
305
306 pci_write_config32(k8_f3, 0x70, 0x51220111);
307 pci_write_config32(k8_f3, 0x74, 0x50404021);
308 pci_write_config32(k8_f3, 0x78, 0x08002A00);
309 if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12)
310 pci_write_config32(k8_f3, 0x7C, 0x0000211A); /* dual core */
311 else
312 pci_write_config32(k8_f3, 0x7C, 0x0000212B); /* single core */
313 set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
314
315 set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
316 set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
317 set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 0 << 10);
318 set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
319 set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
320
321 msr = rdmsr(NB_CFG_MSR);
322 msr.lo &= ~(1 << 9);
323 msr.hi &= ~(1 << 4);
324 wrmsr(NB_CFG_MSR, msr);
325 }
326 #else
327 #define k8_optimization() do {} while (0)
328 #endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
329
330 #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
331 static void fam10_optimization(void)
332 {
333 pci_devfn_t cpu_f0, cpu_f2, cpu_f3;
334 u32 val;
335
336 printk(BIOS_INFO, "fam10_optimization()\n");
337
338 cpu_f0 = PCI_DEV(0, 0x18, 0);
339 cpu_f2 = PCI_DEV(0, 0x18, 2);
340 cpu_f3 = PCI_DEV(0, 0x18, 3);
341
342 /* 8.6.4.1 */
343 /* Table 8-13 */
344 pci_write_config32(cpu_f0, 0x90, 0x808502D0);
345 /* Table 8-14 */
346 pci_write_config32(cpu_f0, 0x94, 0x00000000);
347
348 /* Table 8-15 */
349 val = pci_read_config32(cpu_f0, 0x68);
350 val |= 1 << 24;
351 pci_write_config32(cpu_f0, 0x68, val);
352
353 /* Table 8-16 */
354 val = pci_read_config32(cpu_f0, 0x84);
355 val &= ~(1 << 12);
356 pci_write_config32(cpu_f0, 0x84, val);
357
358 /* Table 8-17 */
359 val = pci_read_config32(cpu_f2, 0x90);
360 val &= ~(1 << 10);
361 pci_write_config32(cpu_f2, 0x90, val);
362
363 /* Table 8-18 */
364 pci_write_config32(cpu_f3, 0x6C, 0x60018051);
365 /* Table 8-19 */
366 pci_write_config32(cpu_f3, 0x70, 0x60321151);
367 /* Table 8-20 */
368 pci_write_config32(cpu_f3, 0x74, 0x00980101);
369 /* Table 8-21 */
370 pci_write_config32(cpu_f3, 0x78, 0x00200C14);
371 /* Table 8-22 */
372 pci_write_config32(cpu_f3, 0x7C, 0x00070811); /* TODO: Check if L3 Cache is enabled. */
373
374 /* Table 8-23 */
375 Set_NB32(cpu_f3, 0x140, 0x00D33656);
376 /* Table 8-24 */
377 Set_NB32(cpu_f3, 0x144, 0x00000036);
378 /* Table 8-25 */
379 Set_NB32(cpu_f3, 0x148, 0x8000832A);
380 /* Table 8-26 */
381 Set_NB32(cpu_f3, 0x158, 0);
382 /* L3 Disabled: L3 Enabled: */
383 /* cores: 2 3 4 2 3 4 */
384 /* bit8:4 28 26 24 24 20 16 */
385 if (!l3_cache()) {
386 Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (24 + 2*(4-cpu_core_number())) << 4 | 2);
387 } else {
388 Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (16 + 4*(4-cpu_core_number())) << 4 | 4);
389 }
390 }
391 #else
392 #define fam10_optimization() do {} while (0)
393 #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
394
395 /*****************************************
396 * rs780_por_pcicfg_init()
397 *****************************************/
398 static void rs780_por_pcicfg_init(pci_devfn_t nb_dev)
399 {
400 /* enable PCI Memory Access */
401 set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02);
402 /* Set RCRB Enable */
403 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x1);
404 /* allow decode of 640k-1MB */
405 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xEF), 0x10);
406 /* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */
407 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x4);
408 /* Power Management Register Enable */
409 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80);
410
411 /* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge
412 * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
413 * BMMsgEn */
414 set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1);
415
416 /* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
417 * Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */
418 set_nbcfg_enable_bits_8(nb_dev, 0x4E, (u8)(~0xFF), 0x05);
419 /* Reg94h[4:0] = 0x0 P drive strength offset 0
420 * Reg94h[6:5] = 0x2 P drive strength additive adjust */
421 set_nbcfg_enable_bits_8(nb_dev, 0x94, (u8)(~0x80), 0x40);
422
423 /* Reg94h[20:16] = 0x0 N drive strength offset 0
424 * Reg94h[22:21] = 0x2 N drive strength additive adjust */
425 set_nbcfg_enable_bits_8(nb_dev, 0x96, (u8)(~0x80), 0x40);
426
427 /* Reg80h[4:0] = 0x0 Termination offset
428 * Reg80h[6:5] = 0x2 Termination additive adjust */
429 set_nbcfg_enable_bits_8(nb_dev, 0x80, (u8)(~0x80), 0x40);
430
431 /* Reg80h[14] = 0x1 Enable receiver termination control */
432 set_nbcfg_enable_bits_8(nb_dev, 0x81, (u8)(~0xFF), 0x40);
433
434 /* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on
435 * Reg94h[14] = 0x1 Enable drive strength control */
436 set_nbcfg_enable_bits_8(nb_dev, 0x95, (u8)(~0x3F), 0xC4);
437
438 /* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */
439 set_nbcfg_enable_bits_8(nb_dev, 0x97, (u8)(~0x1F), 0xE0);
440
441 /* Reg8Ch[9] enables Gfx Debug BAR programming
442 * Reg8Ch[10] enables Gfx Debug BAR operation
443 * Enable programming of the debug bar now, but enable
444 * operation only after it has been programmed */
445 set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x02);
446 }
447
448 static void rs780_por_mc_index_init(pci_devfn_t nb_dev)
449 {
450 set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F);
451 set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060);
452 set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060);
453 set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000);
454 set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000);
455 set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E);
456 set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E);
457 }
458
459 static void rs780_por_misc_index_init(pci_devfn_t nb_dev)
460 {
461 /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
462 * Block non-snoop DMA request if PMArbDis is set.
463 * Set BMSetDis */
464 set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180);
465 set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040);
466
467 /* NBCFG (NBMISCIND 0x0): NB_CNTL -
468 * HIDE_NB_AGP_CAP ([0], default=1)HIDE
469 * HIDE_P2P_AGP_CAP ([1], default=1)HIDE
470 * HIDE_NB_GART_BAR ([2], default=1)HIDE
471 * AGPMODE30 ([4], default=0)DISABLE
472 * AGP30ENCHANCED ([5], default=0)DISABLE
473 * HIDE_AGP_CAP ([8], default=1)ENABLE */
474 set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */
475
476 /* NBMISCIND:0x6A[16]= 1 SB link can get a full swing
477 * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000);
478 * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */
479 set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000);
480
481 /* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */
482 set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500);
483
484 /* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */
485 set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000);
486
487 /* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */
488 set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008);
489
490 /*
491 * Enable access to DEV8
492 * Enable setPower message for all ports
493 */
494 set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6);
495 set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20);
496 set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20);
497 set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20);
498 set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20);
499 set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20);
500 set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20);
501 set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20);
502 set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20, 1 << 20);
503 set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20, 1 << 20);
504
505 set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
506 set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30);
507
508 set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x48);
509 /* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */
510 set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180);
511 }
512
513 /*****************************************
514 * Some setting is from rpr. Some is from CIMx.
515 *****************************************/
516 static void rs780_por_htiu_index_init(pci_devfn_t nb_dev)
517 {
518 #if 0 /* get from rpr. */
519 set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17);
520 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<0, 0x0<<0);
521 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<1, 0x1<<1);
522 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<9, 0x1<<9);
523 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<13, 0x1<<13);
524 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<17, 0x1<<17);
525 set_htiu_enable_bits(nb_dev, 0x06, 0x3<<15, 0x3<<15);
526 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<25, 0x1<<25);
527 set_htiu_enable_bits(nb_dev, 0x06, 0x1<<30, 0x1<<30);
528
529 set_htiu_enable_bits(nb_dev, 0x07, 0x1<<0, 0x1<<0);
530 set_htiu_enable_bits(nb_dev, 0x07, 0x1<<1, 0x0<<1);
531 set_htiu_enable_bits(nb_dev, 0x07, 0x1<<2, 0x0<<2);
532 set_htiu_enable_bits(nb_dev, 0x07, 0x1<<15, 0x1<<15);
533
534 set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<0, 0x1<<0);
535 set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<2, 0x2<<2);
536 set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<4, 0x0<<4);
537
538 /* A12 only */
539 set_htiu_enable_bits(nb_dev, 0x2D, 0x1<<4, 0x1<<4);
540 set_htiu_enable_bits(nb_dev, 0x2D, 0x1<<6, 0x1<<6);
541 set_htiu_enable_bits(nb_dev, 0x05, 0x1<<2, 0x1<<2);
542
543 set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF);
544 #else /* get from CIM. It is more reliable than above. */
545 set_htiu_enable_bits(nb_dev, 0x05, (1<<10|1<<9), 1<<10 | 1<<9);
546 set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x04203A202);
547
548 set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x8001/* | 7 << 8 */); /* fam 10 */
549
550 set_htiu_enable_bits(nb_dev, 0x15, ~0xFFFFFFFF, 1<<31| 1<<30 | 1<<27);
551 set_htiu_enable_bits(nb_dev, 0x1C, ~0xFFFFFFFF, 0xFFFE0000);
552
553 set_htiu_enable_bits(nb_dev, 0x4B, (1<<11), 1<<11);
554
555 set_htiu_enable_bits(nb_dev, 0x0C, ~0xFFFFFFC0, 1<<0|1<<3);
556
557 set_htiu_enable_bits(nb_dev, 0x17, (1<<27|1<<1), 0x1<<1);
558 set_htiu_enable_bits(nb_dev, 0x17, 0x1 << 30, 0x1<<30);
559
560 set_htiu_enable_bits(nb_dev, 0x19, (0xFFFFF+(1<<31)), 0x186A0+(1<<31));
561
562 set_htiu_enable_bits(nb_dev, 0x16, (0x3F<<10), 0x7<<10);
563
564 set_htiu_enable_bits(nb_dev, 0x23, 0xFFFFFFF, 1<<28);
565
566 set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF);
567 #endif
568 }
569
570 /*****************************************
571 * Configure RS780 registers to power-on default RPR.
572 * POR: Power On Reset
573 * RPR: Register Programming Requirements
574 *****************************************/
575 static void rs780_por_init(pci_devfn_t nb_dev)
576 {
577 printk(BIOS_INFO, "rs780_por_init\n");
578 /* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */
579 rs780_por_pcicfg_init(nb_dev);
580
581 /* ATINB_MCIND_POR_TABLE */
582 rs780_por_mc_index_init(nb_dev);
583
584 /* ATINB_MISCIND_POR_TABLE */
585 rs780_por_misc_index_init(nb_dev);
586
587 /* ATINB_HTIUNBIND_POR_TABLE */
588 rs780_por_htiu_index_init(nb_dev);
589
590 /* ATINB_CLKCFG_PORT_TABLE */
591 /* rs780 A11 SB Link full swing? */
592
593 /* SET NB_MISC_REG01 BIT8 to Enable HDMI, reference CIMX_5_9_3 NBPOR_InitPOR(),
594 * then the accesses to internal graphics IO space 0x60/0x64, are forwarded to
595 * nbconfig:0x60/0x64
596 */
597
598 set_nbmisc_enable_bits(nb_dev, 0x01, ~(1 << 8), (1 << 8));
599 }
600
601 /* enable CFG access to Dev8, which is the SB P2P Bridge */
602 void enable_rs780_dev8(void)
603 {
604 set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
605 }
606
607 void rs780_early_setup(void)
608 {
609 pci_devfn_t nb_dev = PCI_DEV(0, 0, 0);
610 printk(BIOS_INFO, "rs780_early_setup()\n");
611
612 /* The printk(BIOS_INFO, s) below cause the system unstable. */
613 switch (get_nb_rev(nb_dev)) {
614 case REV_RS780_A11:
615 /* printk(BIOS_INFO, "NB Revision is A11.\n"); */
616 break;
617 case REV_RS780_A12:
618 /* printk(BIOS_INFO, "NB Revision is A12.\n"); */
619 break;
620 case REV_RS780_A13:
621 /* printk(BIOS_INFO, "NB Revision is A13.\n"); */
622 break;
623 }
624
625 if (is_famly10())
626 fam10_optimization();
627 else
628 k8_optimization();
629
630 rs780_por_init(nb_dev);
631 }
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