src/mainboard/msi/ms9652_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #define FAM10_SCAN_PCI_BUS 0
  19 #define FAM10_ALLOCATE_IO_RANGE 1
  20
  21 #include <stdint.h>
  22 #include <string.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <cpu/x86/lapic.h>
  28 #include <console/console.h>
  29 #include <timestamp.h>
  30 #include <lib.h>
  31 #include <spd.h>
  32 #include <cpu/amd/model_10xxx_rev.h>
  33 #include <delay.h>
  34 #include <cpu/x86/lapic.h>
  35 #include <cpu/amd/car.h>
  36 #include <cpu/amd/msr.h>
  37 #include <superio/winbond/common/winbond.h>
  38 #include <superio/winbond/w83627ehg/w83627ehg.h>
  39 #include <cpu/x86/bist.h>
  40 #include <northbridge/amd/amdfam10/raminit.h>
  41 #include <northbridge/amd/amdht/ht_wrapper.h>
  42 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
  43 #include <arch/early_variables.h>
  44 #include <cbmem.h>
  45 #include <southbridge/nvidia/mcp55/mcp55.h>
  46
  47 #include "resourcemap.c"
  48 #include "cpu/amd/quadcore/quadcore.c"
  49
  50 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  51
  52 void activate_spd_rom(const struct mem_controller *ctrl);
  53 int spd_read_byte(unsigned int device, unsigned int address);
  54 extern struct sys_info sysinfo_car;
  55
  56 void activate_spd_rom(const struct mem_controller *ctrl) { }
  57
  58 inline int spd_read_byte(unsigned int device, unsigned int address)
  59 {
  60         return smbus_read_byte(device, address);
  61 }
  62
  63 unsigned get_sbdn(unsigned bus)
  64 {
  65         pci_devfn_t dev;
  66
  67         /* Find the device. */
  68         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
  69                                        PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
  70
  71         return (dev >> 15) & 0x1f;
  72 }
  73
  74 #define MCP55_MB_SETUP \
  75         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
  76         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
  77         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
  78         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
  79         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
  80         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
  81
  82 #include <southbridge/nvidia/mcp55/early_setup_ss.h>
  83 #include "southbridge/nvidia/mcp55/early_setup_car.c"
  84
  85 static void sio_setup(void)
  86 {
  87         u32 dword;
  88         u8 byte;
  89
  90         byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
  91         byte |= 0x20;
  92         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
  93
  94         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
  95         dword |= (1 << 0);
  96         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
  97 }
  98
  99 static const u8 spd_addr[] = {
 100         //first node
 101         RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
 102 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 103         //second node
 104         RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
 105 #endif
 106 };
 107
 108 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 109 {
 110         struct sys_info *sysinfo = &sysinfo_car;
 111         u32 bsp_apicid = 0, val, wants_reset;
 112         u8 reg;
 113         msr_t msr;
 114
 115         timestamp_init(timestamp_get());
 116         timestamp_add_now(TS_START_ROMSTAGE);
 117
 118         if (!cpu_init_detectedx && boot_cpu()) {
 119                 /* Nothing special needs to be done to find bus 0 */
 120                 /* Allow the HT devices to be found */
 121                 set_bsp_node_CHtExtNodeCfgEn();
 122                 enumerate_ht_chain();
 123                 sio_setup();
 124         }
 125
 126         post_code(0x30);
 127
 128         if (bist == 0)
 129                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 130
 131         post_code(0x32);
 132
 133         pnp_enter_conf_state(SERIAL_DEV);
 134         /* We have 24MHz input. */
 135         reg = pnp_read_config(SERIAL_DEV, 0x24);
 136         pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
 137         pnp_exit_conf_state(SERIAL_DEV);
 138
 139         winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 140         console_init();
 141
 142         /* Halt if there was a built in self test failure */
 143         report_bist_failure(bist);
 144
 145         val = cpuid_eax(1);
 146         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 147         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 148         printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
 149         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 150
 151         /* Setup sysinfo defaults */
 152         set_sysinfo_in_ram(0);
 153
 154         update_microcode(val);
 155
 156         post_code(0x33);
 157
 158         cpuSetAMDMSR(0);
 159         post_code(0x34);
 160
 161         amd_ht_init(sysinfo);
 162         post_code(0x35);
 163
 164         /* Setup nodes PCI space and start core 0 AP init. */
 165         finalize_node_setup(sysinfo);
 166         printk(BIOS_DEBUG, "finalize_node_setup done\n");
 167
 168         /* Setup any mainboard PCI settings etc. */
 169         printk(BIOS_DEBUG, "setup_mb_resource_map begin\n");
 170         setup_mb_resource_map();
 171         printk(BIOS_DEBUG, "setup_mb_resource_map end\n");
 172         post_code(0x36);
 173
 174         /* wait for all the APs core0 started by finalize_node_setup. */
 175         /* FIXME: A bunch of cores are going to start output to serial at once.
 176          * It would be nice to fixup prink spinlocks for ROM XIP mode.
 177          * I think it could be done by putting the spinlock flag in the cache
 178          * of the BSP located right after sysinfo.
 179          */
 180         wait_all_core0_started();
 181
 182 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 183         /* Core0 on each node is configured. Now setup any additional cores. */
 184         printk(BIOS_DEBUG, "start_other_cores()\n");
 185         start_other_cores(bsp_apicid);
 186         post_code(0x37);
 187         printk(BIOS_DEBUG, "wait_all_other_cores_started()\n");
 188         wait_all_other_cores_started(bsp_apicid);
 189 #endif
 190
 191         post_code(0x38);
 192
 193 #if IS_ENABLED(CONFIG_SET_FIDVID)
 194         msr = rdmsr(MSR_COFVID_STS);
 195         printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 196
 197         /* FIXME: The sb fid change may survive the warm reset and only
 198          * need to be done once.*/
 199         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 200
 201         post_code(0x39);
 202
 203         if (!warm_reset_detect(0)) {                    // BSP is node 0
 204                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 205         } else {
 206                 init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0
 207         }
 208
 209         post_code(0x3A);
 210
 211         /* show final fid and vid */
 212         msr = rdmsr(MSR_COFVID_STS);
 213         printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 214 #endif
 215         init_timer(); /* Need to use TMICT to synchronize FID/VID. */
 216
 217         wants_reset = mcp55_early_setup_x();
 218
 219         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 220         if (!warm_reset_detect(0)) {
 221                 printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 222                 soft_reset();
 223                 die("After soft_reset - shouldn't see this message!!!\n");
 224         }
 225
 226         if (wants_reset)
 227                 printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 228
 229         post_code(0x3B);
 230
 231         /* It's the time to set ctrl in sysinfo now; */
 232         printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 233         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 234         post_code(0x3D);
 235
 236         printk(BIOS_DEBUG, "enable_smbus()\n");
 237         enable_smbus();
 238
 239         post_code(0x40);
 240
 241         timestamp_add_now(TS_BEFORE_INITRAM);
 242         printk(BIOS_DEBUG, "raminit_amdmct()\n");
 243         raminit_amdmct(sysinfo);
 244         timestamp_add_now(TS_AFTER_INITRAM);
 245
 246         cbmem_initialize_empty();
 247         post_code(0x41);
 248
 249         amdmct_cbmem_store_info(sysinfo);
 250 }
 251
 252 /**
 253  * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
 254  * Description:
 255  *      This routine is called every time a non-coherent chain is processed.
 256  *      BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
 257  *      swap list. The first part of the list controls the BUID assignment and the
 258  *      second part of the list provides the device to device linking.  Device orientation
 259  *      can be detected automatically, or explicitly.  See documentation for more details.
 260  *
 261  *      Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 262  *      based on each device's unit count.
 263  *
 264  * Parameters:
 265  *      @param[in]  node   = The node on which this chain is located
 266  *      @param[in]  link   = The link on the host for this chain
 267  *      @param[out] List   = supply a pointer to a list
 268  */
 269 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 270 {
 271         static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 272         /* If the BUID was adjusted in early_ht we need to do the manual override */
 273         if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
 274                 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 275                 if ((node == 0) && (link == 0)) {       /* BSP SB link */
 276                         *List = swaplist;
 277                         return 1;
 278                 }
 279         }
 280
 281         return 0;
 282 }