2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 //#define SYSTEM_TYPE 0 /* SERVER */
17 #define SYSTEM_TYPE 1 /* DESKTOP */
18 //#define SYSTEM_TYPE 2 /* MOBILE */
20 #define FAM10_SCAN_PCI_BUS 0
21 #define FAM10_ALLOCATE_IO_RANGE 0
25 #include <device/pci_def.h>
26 #include <device/pci_ids.h>
28 #include <device/pnp_def.h>
29 #include <cpu/x86/lapic.h>
30 #include <console/console.h>
31 #include <timestamp.h>
32 #include <cpu/amd/model_10xxx_rev.h>
34 #include <cpu/x86/lapic.h>
35 #include <commonlib/loglevel.h>
36 #include <cpu/x86/bist.h>
37 #include <superio/fintek/common/fintek.h>
38 #include <superio/fintek/f71859/f71859.h>
39 #include <cpu/amd/msr.h>
40 #include <cpu/amd/mtrr.h>
41 #include <cpu/amd/car.h>
42 #include <southbridge/amd/sb700/sb700.h>
43 #include <southbridge/amd/sb700/smbus.h>
45 #include <northbridge/amd/amdfam10/raminit.h>
46 #include <northbridge/amd/amdht/ht_wrapper.h>
47 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
48 #include <arch/early_variables.h>
50 #include <southbridge/amd/rs780/rs780.h>
52 #include "resourcemap.c"
53 #include "cpu/amd/quadcore/quadcore.c"
55 #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
57 void activate_spd_rom(const struct mem_controller
*ctrl
);
58 int spd_read_byte(unsigned int device
, unsigned int address
);
59 extern struct sys_info sysinfo_car
;
61 void activate_spd_rom(const struct mem_controller
*ctrl
) { }
63 int spd_read_byte(u32 device
, u32 address
)
65 return do_smbus_read_byte(SMBUS_IO_BASE
, device
, address
);
68 void cache_as_ram_main(unsigned long bist
, unsigned long cpu_init_detectedx
)
70 struct sys_info
*sysinfo
= &sysinfo_car
;
71 static const u8 spd_addr
[] = {RC00
, DIMM0
, DIMM2
, 0, 0, DIMM1
, DIMM3
, 0, 0, };
72 u32 bsp_apicid
= 0, val
;
75 timestamp_init(timestamp_get());
76 timestamp_add_now(TS_START_ROMSTAGE
);
78 if (!cpu_init_detectedx
&& boot_cpu()) {
79 /* Nothing special needs to be done to find bus 0 */
80 /* Allow the HT devices to be found */
81 /* mov bsp to bus 0xff when > 8 nodes */
82 set_bsp_node_CHtExtNodeCfgEn();
84 sb7xx_51xx_pci_port80();
90 bsp_apicid
= init_cpus(cpu_init_detectedx
, sysinfo
); /* mmconf is inited in init_cpus */
91 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
97 sb7xx_51xx_lpc_init();
99 fintek_enable_serial(SERIAL_DEV
, CONFIG_TTYS0_BASE
);
103 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
105 /* Halt if there was a built in self test failure */
106 report_bist_failure(bist
);
110 printk(BIOS_DEBUG
, "BSP Family_Model: %08x\n", val
);
111 printk(BIOS_DEBUG
, "*sysinfo range: [%p,%p]\n",sysinfo
,sysinfo
+1);
112 printk(BIOS_DEBUG
, "bsp_apicid = %02x\n", bsp_apicid
);
113 printk(BIOS_DEBUG
, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx
);
115 /* Setup sysinfo defaults */
116 set_sysinfo_in_ram(0);
118 update_microcode(val
);
125 amd_ht_init(sysinfo
);
128 /* Setup nodes PCI space and start core 0 AP init. */
129 finalize_node_setup(sysinfo
);
131 /* Setup any mainboard PCI settings etc. */
132 setup_mb_resource_map();
135 /* wait for all the APs core0 started by finalize_node_setup. */
136 /* FIXME: A bunch of cores are going to start output to serial at once.
137 It would be nice to fixup prink spinlocks for ROM XIP mode.
138 I think it could be done by putting the spinlock flag in the cache
139 of the BSP located right after sysinfo.
141 wait_all_core0_started();
143 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
144 /* Core0 on each node is configured. Now setup any additional cores. */
145 printk(BIOS_DEBUG
, "start_other_cores()\n");
146 start_other_cores(bsp_apicid
);
148 wait_all_other_cores_started(bsp_apicid
);
153 /* run _early_setup before soft-reset. */
155 sb7xx_51xx_early_setup();
157 #if IS_ENABLED(CONFIG_SET_FIDVID)
158 msr
= rdmsr(MSR_COFVID_STS
);
159 printk(BIOS_DEBUG
, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr
.hi
, msr
.lo
);
161 /* FIXME: The sb fid change may survive the warm reset and only
162 need to be done once.*/
163 enable_fid_change_on_sb(sysinfo
->sbbusn
, sysinfo
->sbdn
);
167 if (!warm_reset_detect(0)) { // BSP is node 0
168 init_fidvid_bsp(bsp_apicid
, sysinfo
->nodes
);
170 init_fidvid_stage2(bsp_apicid
, 0); // BSP is node 0
175 /* show final fid and vid */
176 msr
= rdmsr(MSR_COFVID_STS
);
177 printk(BIOS_DEBUG
, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr
.hi
, msr
.lo
);
182 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
183 if (!warm_reset_detect(0)) {
184 printk(BIOS_INFO
, "...WARM RESET...\n\n\n");
186 die("After soft_reset - shouldn't see this message!!!\n");
191 /* It's the time to set ctrl in sysinfo now; */
192 printk(BIOS_DEBUG
, "fill_mem_ctrl()\n");
193 fill_mem_ctrl(sysinfo
->nodes
, sysinfo
->ctrl
, spd_addr
);
197 // die("Die Before MCT init.");
199 timestamp_add_now(TS_BEFORE_INITRAM
);
200 printk(BIOS_DEBUG
, "raminit_amdmct()\n");
201 raminit_amdmct(sysinfo
);
202 timestamp_add_now(TS_AFTER_INITRAM
);
204 cbmem_initialize_empty();
207 amdmct_cbmem_store_info(sysinfo
);
210 dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
211 dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
212 dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
213 dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
216 // die("After MCT init before CAR disabled.");
218 sb7xx_51xx_before_pci_init();
224 * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
226 * This routine is called every time a non-coherent chain is processed.
227 * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
228 * swap list. The first part of the list controls the BUID assignment and the
229 * second part of the list provides the device to device linking. Device orientation
230 * can be detected automatically, or explicitly. See documentation for more details.
232 * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
233 * based on each device's unit count.
236 * @param[in] node = The node on which this chain is located
237 * @param[in] link = The link on the host for this chain
238 * @param[out] List = supply a pointer to a list
240 BOOL
AMD_CB_ManualBUIDSwapList (u8 node
, u8 link
, const u8
**List
)
242 static const u8 swaplist
[] = {0, 1, 0xFF, 0, 0xFF};
243 /* If the BUID was adjusted in early_ht we need to do the manual override */
244 if ((node
== 0) && (link
== 0)) { /* BSP SB link */