src/mainboard/hp/dl165_g6_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2007 University of Mannheim
   9  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
  10  * Copyright (C) 2009 University of Heidelberg
  11  * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  */
  23
  24 #define FAM10_SCAN_PCI_BUS 0
  25 #define FAM10_ALLOCATE_IO_RANGE 1
  26
  27 #include <stdint.h>
  28 #include <string.h>
  29 #include <device/pci_def.h>
  30 #include <device/pci_ids.h>
  31 #include <arch/io.h>
  32 #include <device/pnp_def.h>
  33 #include <cpu/x86/lapic.h>
  34 #include "option_table.h"
  35 #include <console/console.h>
  36 #include <timestamp.h>
  37 #include <cpu/amd/model_10xxx_rev.h>
  38 #include <lib.h>
  39 #include <spd.h>
  40 #include <delay.h>
  41 #include <cpu/x86/lapic.h>
  42 #include <superio/serverengines/pilot/pilot.h>
  43 #include <superio/nsc/pc87417/pc87417.h>
  44 #include <cpu/x86/bist.h>
  45 #include <cpu/amd/car.h>
  46 #include <cpu/amd/msr.h>
  47 #include <northbridge/amd/amdfam10/raminit.h>
  48 #include <northbridge/amd/amdht/ht_wrapper.h>
  49 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
  50 #include <arch/early_variables.h>
  51 #include <cbmem.h>
  52 #include "southbridge/broadcom/bcm5785/early_smbus.c"
  53 #include "southbridge/broadcom/bcm5785/early_setup.c"
  54
  55 #include "cpu/amd/quadcore/quadcore.c"
  56
  57 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
  58 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
  59
  60 void activate_spd_rom(const struct mem_controller *ctrl);
  61 int spd_read_byte(unsigned int device, unsigned int address);
  62 extern struct sys_info sysinfo_car;
  63
  64 inline void activate_spd_rom(const struct mem_controller *ctrl)
  65 {
  66         u8 val;
  67         outb(0x3d, 0x0cd6);
  68         outb(0x87, 0x0cd7);
  69
  70         outb(0x44, 0xcd6);
  71         val = inb(0xcd7);
  72         outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7);
  73 }
  74
  75 inline int spd_read_byte(unsigned int device, unsigned int address)
  76 {
  77         return smbus_read_byte(device, address);
  78 }
  79
  80 static const u8 spd_addr[] = {
  81         // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr
  82         //first node
  83         RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
  84 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  85         //second node
  86         RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
  87 #endif
  88 };
  89
  90 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  91 {
  92         struct sys_info *sysinfo = &sysinfo_car;
  93         u32 bsp_apicid = 0, val;
  94         msr_t msr;
  95
  96         timestamp_init(timestamp_get());
  97         timestamp_add_now(TS_START_ROMSTAGE);
  98
  99         if (!cpu_init_detectedx && boot_cpu()) {
 100                 /* Nothing special needs to be done to find bus 0 */
 101                 /* Allow the HT devices to be found */
 102                 /* mov bsp to bus 0xff when > 8 nodes */
 103                 set_bsp_node_CHtExtNodeCfgEn();
 104                 enumerate_ht_chain();
 105                 bcm5785_enable_lpc();
 106                 pc87417_enable_dev(RTC_DEV); /* Enable RTC */
 107         }
 108
 109         post_code(0x30);
 110
 111         if (bist == 0)
 112                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 113
 114         pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 115
 116         console_init();
 117
 118         /* Halt if there was a built in self test failure */
 119         report_bist_failure(bist);
 120
 121         pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 122
 123         val = cpuid_eax(1);
 124         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 125         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 126         printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
 127         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 128
 129         /* Setup sysinfo defaults */
 130         set_sysinfo_in_ram(0);
 131
 132         update_microcode(val);
 133
 134         post_code(0x33);
 135
 136         cpuSetAMDMSR(0);
 137         post_code(0x34);
 138
 139         amd_ht_init(sysinfo);
 140         post_code(0x35);
 141
 142         /* Setup nodes PCI space and start core 0 AP init. */
 143         finalize_node_setup(sysinfo);
 144
 145         post_code(0x36);
 146
 147         /* wait for all the APs core0 started by finalize_node_setup. */
 148         /* FIXME: A bunch of cores are going to start output to serial at once.
 149          * It would be nice to fixup prink spinlocks for ROM XIP mode.
 150          * I think it could be done by putting the spinlock flag in the cache
 151          * of the BSP located right after sysinfo.
 152          */
 153
 154         wait_all_core0_started();
 155
 156 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 157         /* Core0 on each node is configured. Now setup any additional cores. */
 158         printk(BIOS_DEBUG, "start_other_cores()\n");
 159         start_other_cores(bsp_apicid);
 160         post_code(0x37);
 161         wait_all_other_cores_started(bsp_apicid);
 162 #endif
 163
 164 #if IS_ENABLED(CONFIG_SET_FIDVID)
 165         msr = rdmsr(MSR_COFVID_STS);
 166         printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 167
 168         /* FIXME: The sb fid change may survive the warm reset and only
 169          * need to be done once.*/
 170
 171         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 172
 173         post_code(0x39);
 174
 175         if (!warm_reset_detect(0)) {                    // BSP is node 0
 176                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 177         } else {
 178                 init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0
 179         }
 180
 181         post_code(0x3A);
 182
 183         /* show final fid and vid */
 184         msr = rdmsr(MSR_COFVID_STS);
 185         printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 186 #endif
 187
 188         init_timer();
 189
 190         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 191         if (!warm_reset_detect(0)) {
 192                 printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 193                 soft_reset();
 194                 die("After soft_reset - shouldn't see this message!!!\n");
 195         }
 196
 197         /* It's the time to set ctrl in sysinfo now; */
 198         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 199         enable_smbus();
 200
 201         //do we need apci timer, tsc...., only debug need it for better output
 202         /* all ap stopped? */
 203 //      init_timer(); // Need to use TMICT to synchronize FID/VID
 204
 205         timestamp_add_now(TS_BEFORE_INITRAM);
 206         printk(BIOS_DEBUG, "raminit_amdmct()\n");
 207         raminit_amdmct(sysinfo);
 208         timestamp_add_now(TS_AFTER_INITRAM);
 209
 210         cbmem_initialize_empty();
 211         post_code(0x41);
 212
 213         amdmct_cbmem_store_info(sysinfo);
 214
 215         bcm5785_early_setup();
 216 }
 217
 218 /**
 219  * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
 220  * Description:
 221  *      This routine is called every time a non-coherent chain is processed.
 222  *      BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
 223  *      swap list. The first part of the list controls the BUID assignment and the
 224  *      second part of the list provides the device to device linking.  Device orientation
 225  *      can be detected automatically, or explicitly.  See documentation for more details.
 226  *
 227  *      Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 228  *      based on each device's unit count.
 229  *
 230  * Parameters:
 231  *      @param[in]  node   = The node on which this chain is located
 232  *      @param[in]  link   = The link on the host for this chain
 233  *      @param[out] List   = supply a pointer to a list
 234  */
 235 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 236 {
 237         static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 238         /* If the BUID was adjusted in early_ht we need to do the manual override */
 239         if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
 240                 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 241                 if ((node == 0) && (link == 0)) {       /* BSP SB link */
 242                         *List = swaplist;
 243                         return 1;
 244                 }
 245         }
 246
 247         return 0;
 248 }