src/mainboard/gigabyte/ma785gm/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 //#define SYSTEM_TYPE 0 /* SERVER */
  17 #define SYSTEM_TYPE 1   /* DESKTOP */
  18 //#define SYSTEM_TYPE 2 /* MOBILE */
  19
  20 #include <stdint.h>
  21 #include <string.h>
  22 #include <device/pci_def.h>
  23 #include <device/pci_ids.h>
  24 #include <arch/io.h>
  25 #include <device/pnp_def.h>
  26 #include <cpu/x86/lapic.h>
  27 #include <console/console.h>
  28 #include <timestamp.h>
  29 #include <cpu/amd/model_10xxx_rev.h>
  30 #include <lib.h>
  31 #include <cpu/x86/lapic.h>
  32 #include <commonlib/loglevel.h>
  33 #include <cpu/x86/bist.h>
  34 #include <superio/ite/common/ite.h>
  35 #include <superio/ite/it8718f/it8718f.h>
  36 #include <cpu/amd/msr.h>
  37 #include <cpu/amd/mtrr.h>
  38 #include <cpu/amd/car.h>
  39 #include <southbridge/amd/sb700/sb700.h>
  40 #include <southbridge/amd/sb700/smbus.h>
  41 #include <northbridge/amd/amdfam10/raminit.h>
  42 #include <northbridge/amd/amdht/ht_wrapper.h>
  43 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
  44 #include <arch/early_variables.h>
  45 #include <cbmem.h>
  46 #include <spd.h>
  47 #include <southbridge/amd/rs780/rs780.h>
  48
  49 #include "resourcemap.c"
  50 #include "cpu/amd/quadcore/quadcore.c"
  51
  52 #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
  53 #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
  54
  55 void activate_spd_rom(const struct mem_controller *ctrl);
  56 int spd_read_byte(unsigned int device, unsigned int address);
  57 extern struct sys_info sysinfo_car;
  58
  59 void activate_spd_rom(const struct mem_controller *ctrl) { }
  60
  61 int spd_read_byte(u32 device, u32 address)
  62 {
  63         return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
  64 }
  65
  66 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  67 {
  68         struct sys_info *sysinfo = &sysinfo_car;
  69         static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
  70         u32 bsp_apicid = 0, val;
  71         msr_t msr;
  72
  73         timestamp_init(timestamp_get());
  74         timestamp_add_now(TS_START_ROMSTAGE);
  75
  76         if (!cpu_init_detectedx && boot_cpu()) {
  77                 /* Nothing special needs to be done to find bus 0 */
  78                 /* Allow the HT devices to be found */
  79                 /* mov bsp to bus 0xff when > 8 nodes */
  80                 set_bsp_node_CHtExtNodeCfgEn();
  81                 enumerate_ht_chain();
  82                 sb7xx_51xx_pci_port80();
  83         }
  84
  85         post_code(0x30);
  86
  87         if (bist == 0) {
  88                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
  89                 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
  90         }
  91
  92         post_code(0x32);
  93
  94         enable_rs780_dev8();
  95         sb7xx_51xx_lpc_init();
  96
  97         ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  98         it8718f_disable_reboot(GPIO_DEV);
  99         console_init();
 100
 101 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 102
 103         /* Halt if there was a built in self test failure */
 104         report_bist_failure(bist);
 105
 106         // Load MPB
 107         val = cpuid_eax(1);
 108         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 109         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 110         printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
 111         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 112
 113         /* Setup sysinfo defaults */
 114         set_sysinfo_in_ram(0);
 115
 116         update_microcode(val);
 117
 118         post_code(0x33);
 119
 120         cpuSetAMDMSR(0);
 121         post_code(0x34);
 122
 123         amd_ht_init(sysinfo);
 124         post_code(0x35);
 125
 126         /* Setup nodes PCI space and start core 0 AP init. */
 127         finalize_node_setup(sysinfo);
 128
 129         /* Setup any mainboard PCI settings etc. */
 130         setup_mb_resource_map();
 131         post_code(0x36);
 132
 133         /* wait for all the APs core0 started by finalize_node_setup. */
 134         /* FIXME: A bunch of cores are going to start output to serial at once.
 135            It would be nice to fixup prink spinlocks for ROM XIP mode.
 136            I think it could be done by putting the spinlock flag in the cache
 137            of the BSP located right after sysinfo.
 138          */
 139         wait_all_core0_started();
 140
 141 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 142         /* Core0 on each node is configured. Now setup any additional cores. */
 143         printk(BIOS_DEBUG, "start_other_cores()\n");
 144         start_other_cores(bsp_apicid);
 145         post_code(0x37);
 146         wait_all_other_cores_started(bsp_apicid);
 147 #endif
 148
 149         post_code(0x38);
 150
 151         /* run _early_setup before soft-reset. */
 152         rs780_early_setup();
 153         sb7xx_51xx_early_setup();
 154
 155 #if IS_ENABLED(CONFIG_SET_FIDVID)
 156         msr = rdmsr(MSR_COFVID_STS);
 157         printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 158
 159         /* FIXME: The sb fid change may survive the warm reset and only
 160            need to be done once.*/
 161         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 162
 163         post_code(0x39);
 164
 165         if (!warm_reset_detect(0)) {                    // BSP is node 0
 166                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 167         } else {
 168                 init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0
 169         }
 170
 171         post_code(0x3A);
 172
 173         /* show final fid and vid */
 174         msr = rdmsr(MSR_COFVID_STS);
 175         printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 176 #endif
 177
 178         rs780_htinit();
 179
 180         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 181         if (!warm_reset_detect(0)) {
 182                 printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 183                 soft_reset();
 184                 die("After soft_reset - shouldn't see this message!!!\n");
 185         }
 186
 187         post_code(0x3B);
 188
 189         /* It's the time to set ctrl in sysinfo now; */
 190         printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 191         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 192
 193         post_code(0x40);
 194
 195 //      die("Die Before MCT init.");
 196
 197         timestamp_add_now(TS_BEFORE_INITRAM);
 198         printk(BIOS_DEBUG, "raminit_amdmct()\n");
 199         raminit_amdmct(sysinfo);
 200         timestamp_add_now(TS_AFTER_INITRAM);
 201
 202         cbmem_initialize_empty();
 203         post_code(0x41);
 204
 205         amdmct_cbmem_store_info(sysinfo);
 206
 207 /*
 208         dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
 209         dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
 210         dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
 211         dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 212 */
 213
 214 //      die("After MCT init before CAR disabled.");
 215
 216         sb7xx_51xx_before_pci_init();
 217
 218         post_code(0x42);
 219 }
 220
 221 /**
 222  * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
 223  * Description:
 224  *      This routine is called every time a non-coherent chain is processed.
 225  *      BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
 226  *      swap list. The first part of the list controls the BUID assignment and the
 227  *      second part of the list provides the device to device linking.  Device orientation
 228  *      can be detected automatically, or explicitly.  See documentation for more details.
 229  *
 230  *      Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 231  *      based on each device's unit count.
 232  *
 233  * Parameters:
 234  *      @param[in]   node   = The node on which this chain is located
 235  *      @param[in]   link   = The link on the host for this chain
 236  *      @param[out]  List   = supply a pointer to a list
 237  */
 238 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 239 {
 240         static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 241         /* If the BUID was adjusted in early_ht we need to do the manual override */
 242         if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
 243                 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 244                 if ((node == 0) && (link == 0)) {       /* BSP SB link */
 245                         *List = swaplist;
 246                         return 1;
 247                 }
 248         }
 249
 250         return 0;
 251 }