src/cpu/amd/pi/00660F01/model_15_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2015 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <cpu/x86/msr.h>
  18 #include <cpu/amd/msr.h>
  19 #include <cpu/x86/mtrr.h>
  20 #include <cpu/amd/mtrr.h>
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <string.h>
  24 #include <cpu/x86/pae.h>
  25 #include <pc80/mc146818rtc.h>
  26 #include <cpu/x86/lapic.h>
  27 #include <cpu/cpu.h>
  28 #include <cpu/x86/cache.h>
  29 #include <arch/acpi.h>
  30
  31 #include <amdlib.h>
  32 #include <PspBaseLib.h>
  33
  34 void PSPProgBar3Msr(void *Buffer);
  35
  36 void PSPProgBar3Msr(void *Buffer)
  37 {
  38         u32 Bar3Addr;
  39         u64 Tmp64;
  40         /* Get Bar3 Addr */
  41         Bar3Addr = PspLibPciReadPspConfig(0x20);
  42         Tmp64 = Bar3Addr;
  43         printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);
  44         LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL);
  45         LibAmdMsrRead(0xC00110A2, &Tmp64, NULL);
  46 }
  47
  48 static void model_15_init(struct device *dev)
  49 {
  50         printk(BIOS_DEBUG, "Model 15 Init.\n");
  51
  52         u8 i;
  53         msr_t msr;
  54         int num_banks;
  55         int msrno;
  56 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
  57         u32 siblings;
  58 #endif
  59
  60         disable_cache();
  61         /* Enable access to AMD RdDram and WrDram extension bits */
  62         msr = rdmsr(SYSCFG_MSR);
  63         msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
  64         msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
  65         wrmsr(SYSCFG_MSR, msr);
  66
  67         // BSP: make a0000-bffff UC, c0000-fffff WB
  68         msr.lo = msr.hi = 0;
  69         wrmsr(0x259, msr);
  70         msr.lo = msr.hi = 0x1e1e1e1e;
  71         wrmsr(0x250, msr);
  72         wrmsr(0x258, msr);
  73         for (msrno = 0x268; msrno <= 0x26f; msrno++)
  74                 wrmsr(msrno, msr);
  75
  76         msr = rdmsr(SYSCFG_MSR);
  77         msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
  78         msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
  79         wrmsr(SYSCFG_MSR, msr);
  80
  81         x86_mtrr_check();
  82         x86_enable_cache();
  83
  84         /* zero the machine check error status registers */
  85         msr = rdmsr(IA32_MCG_CAP);
  86         num_banks = msr.lo & MCA_BANKS_MASK;
  87         msr.lo = 0;
  88         msr.hi = 0;
  89         for (i = 0; i < num_banks; i++)
  90                 wrmsr(IA32_MC0_STATUS + (i * 4), msr);
  91
  92         /* Enable the local CPU APICs */
  93         setup_lapic();
  94
  95 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
  96         siblings = cpuid_ecx(0x80000008) & 0xff;
  97
  98         if (siblings > 0) {
  99                 msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
 100                 msr.lo |= 1 << 28;
 101                 wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
 102
 103                 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
 104                 msr.hi |= 1 << (33 - 32);
 105                 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 106         }
 107         printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
 108 #endif
 109         PSPProgBar3Msr(NULL);
 110
 111         /* DisableCf8ExtCfg */
 112         msr = rdmsr(NB_CFG_MSR);
 113         msr.hi &= ~(1 << (46 - 32));
 114         wrmsr(NB_CFG_MSR, msr);
 115
 116
 117         /* Write protect SMM space with SMMLOCK. */
 118         msr = rdmsr(HWCR_MSR);
 119         msr.lo |= (1 << 0);
 120         wrmsr(HWCR_MSR, msr);
 121 }
 122
 123 static struct device_operations cpu_dev_ops = {
 124         .init = model_15_init,
 125 };
 126
 127 static const struct cpu_device_id cpu_table[] = {
 128         { X86_VENDOR_AMD, 0x660f00 },
 129         { X86_VENDOR_AMD, 0x660f01 },
 130         { 0, 0 },
 131 };
 132
 133 static const struct cpu_driver model_15 __cpu_driver = {
 134         .ops      = &cpu_dev_ops,
 135         .id_table = cpu_table,
 136 };