src/cpu/amd/family_10h-family_15h/tsc_freq.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2016 Raptor Engineering
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stdint.h>
  17 #include <cpu/x86/msr.h>
  18 #include <cpu/amd/msr.h>
  19 #include <cpu/x86/tsc.h>
  20
  21 unsigned long tsc_freq_mhz(void)
  22 {
  23         msr_t msr;
  24         uint8_t cpufid;
  25         uint8_t cpudid;
  26
  27         /* On Family 10h/15h CPUs the TSC increments
  28          * at the P0 clock rate.  Read the P0 clock
  29          * frequency from the P0 MSR and convert
  30          * to MHz.  See also the Family 15h BKDG
  31          * Rev. 3.14 page 569.
  32          */
  33         msr = rdmsr(PSTATE_0_MSR);
  34         cpufid = (msr.lo & 0x3f);
  35         cpudid = (msr.lo & 0x1c0) >> 6;
  36
  37         return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
  38 }