src/cpu/amd/car/disable_cache_as_ram.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * original idea yhlu 6.2005 (assembler code)
   5  *
   6  * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
   7  * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
   8  *                    Raptor Engineering
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; version 2 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * WARNING: this file will be used by both any AP cores and core 0 / node 0
  20  */
  21
  22 #include <cpu/x86/cache.h>
  23 #include <cpu/x86/msr.h>
  24 #include <cpu/amd/msr.h>
  25
  26 static __always_inline uint32_t amd_fam1x_cpu_family(void)
  27 {
  28         uint32_t family;
  29
  30         family = cpuid_eax(0x80000001);
  31         family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
  32
  33         return family;
  34 }
  35
  36 static __always_inline
  37 void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
  38 {
  39         msr_t msr;
  40         uint32_t family;
  41
  42         if (!skip_sharedc_config) {
  43                 /* disable cache */
  44                 write_cr0(read_cr0() | CR0_CacheDisable);
  45
  46                 msr.lo = 0;
  47                 msr.hi = 0;
  48                 wrmsr(MTRR_FIX_4K_C8000, msr);
  49                 if (CONFIG_DCACHE_RAM_SIZE > 0x8000)
  50                         wrmsr(MTRR_FIX_4K_C0000, msr);
  51                 if (CONFIG_DCACHE_RAM_SIZE > 0x10000)
  52                         wrmsr(MTRR_FIX_4K_D0000, msr);
  53                 if (CONFIG_DCACHE_RAM_SIZE > 0x18000)
  54                         wrmsr(MTRR_FIX_4K_D8000, msr);
  55
  56                 /* disable fixed mtrr from now on,
  57                  * it will be enabled by ramstage again
  58                  */
  59                 msr = rdmsr(SYSCFG_MSR);
  60                 msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn
  61                         | SYSCFG_MSR_MtrrFixDramModEn);
  62                 wrmsr(SYSCFG_MSR, msr);
  63
  64                 /* Set the default memory type and
  65                  * disable fixed and enable variable MTRRs
  66                  */
  67                 msr.hi = 0;
  68                 msr.lo = (1 << 11);
  69
  70                 wrmsr(MTRR_DEF_TYPE_MSR, msr);
  71
  72                 enable_cache();
  73         }
  74
  75         /* INVDWBINVD = 1 */
  76         msr = rdmsr(HWCR_MSR);
  77         msr.lo |= (0x1 << 4);
  78         wrmsr(HWCR_MSR, msr);
  79
  80         family = amd_fam1x_cpu_family();
  81
  82 #if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
  83         if (family >= 0x6f) {
  84                 /* Family 15h or later */
  85
  86                 /* DisSS = 0 */
  87                 msr = rdmsr(LS_CFG_MSR);
  88                 msr.lo &= ~(0x1 << 28);
  89                 wrmsr(LS_CFG_MSR, msr);
  90
  91                 if (!skip_sharedc_config) {
  92                         /* DisSpecTlbRld = 0 */
  93                         msr = rdmsr(IC_CFG_MSR);
  94                         msr.lo &= ~(0x1 << 9);
  95                         wrmsr(IC_CFG_MSR, msr);
  96
  97                         /* Erratum 714: SpecNbReqDis = 0 */
  98                         msr = rdmsr(BU_CFG2_MSR);
  99                         msr.lo &= ~(0x1 << 8);
 100                         wrmsr(BU_CFG2_MSR, msr);
 101                 }
 102
 103                 /* DisSpecTlbRld = 0 */
 104                 /* DisHwPf = 0 */
 105                 msr = rdmsr(DC_CFG_MSR);
 106                 msr.lo &= ~(0x1 << 4);
 107                 msr.lo &= ~(0x1 << 13);
 108                 wrmsr(DC_CFG_MSR, msr);
 109         }
 110 #endif
 111 }