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soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API
[coreboot.git]
/
configs
/
config.emulation_qemu_riscv_rv64
blob
d41963c15704ffe5b96b2e2b397dd8e2f3d74c4f
1
CONFIG_BOARD_EMULATION_QEMU_RISCV_RV64=y
2
CONFIG_RISCV_OPENSBI=y
