src/northbridge/via/cn700/northbridge.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 VIA Technologies, Inc.
   5  * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
   6  * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <console/console.h>
  20 #include <arch/io.h>
  21 #include <stdint.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include <stdlib.h>
  26 #include <string.h>
  27 #include <lib.h>
  28 #include <cbmem.h>
  29 #include <cpu/cpu.h>
  30 #include "northbridge.h"
  31 #include "cn700.h"
  32
  33 static void memctrl_init(device_t dev)
  34 {
  35         device_t vlink_dev;
  36         u16 reg16;
  37         u8 ranks, pagec, paged, pagee, pagef, shadowreg;
  38
  39         /* Set up the VGA framebuffer size. */
  40         reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15);
  41         pci_write_config16(dev, 0xa0, reg16);
  42
  43         /* Set up VGA timers. */
  44         pci_write_config8(dev, 0xa2, 0x44);
  45
  46         for (ranks = 0x4b; ranks >= 0x48; ranks--) {
  47                 if (pci_read_config8(dev, ranks)) {
  48                         ranks -= 0x48;
  49                         break;
  50                 }
  51         }
  52         if (ranks == 0x47)
  53                 ranks = 0x00;
  54         reg16 = 0xaae0;
  55         reg16 |= ranks;
  56         /* GMINT Misc. FrameBuffer rank */
  57         pci_write_config16(dev, 0xb0, reg16);
  58         /* AGPCINT Misc. */
  59         pci_write_config8(dev, 0xb8, 0x08);
  60
  61         /* Shadow RAM */
  62         pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
  63         /* PAGE C, D, E are all read write enable */
  64         pci_write_config8(dev, 0x80, pagec);
  65         pci_write_config8(dev, 0x81, paged);
  66         pci_write_config8(dev, 0x82, pagee);
  67         /* PAGE F are read/writable */
  68         shadowreg = pci_read_config8(dev, 0x83);
  69         shadowreg |= pagef;
  70         pci_write_config8(dev, 0x83, shadowreg);
  71         /* vlink mirror */
  72         vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
  73                                     PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
  74         if (vlink_dev) {
  75                 pci_write_config8(vlink_dev, 0x61, pagec);
  76                 pci_write_config8(vlink_dev, 0x62, paged);
  77                 pci_write_config8(vlink_dev, 0x64, pagee);
  78
  79                 shadowreg = pci_read_config8(vlink_dev, 0x63);
  80                 shadowreg |= pagef;
  81                 pci_write_config8(vlink_dev, 0x63, shadowreg);
  82         }
  83 }
  84
  85 static const struct device_operations memctrl_operations = {
  86         .read_resources = DEVICE_NOOP,
  87         .init           = memctrl_init,
  88 };
  89
  90 static const struct pci_driver memctrl_driver __pci_driver = {
  91         .ops    = &memctrl_operations,
  92         .vendor = PCI_VENDOR_ID_VIA,
  93         .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
  94 };
  95
  96 static void pci_domain_set_resources(device_t dev)
  97 {
  98         /* The order is important to find the correct RAM size. */
  99         static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
 100         device_t mc_dev;
 101         u32 pci_tolm;
 102
 103         printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");
 104
 105         pci_tolm = find_pci_tolm(dev->link_list);
 106         mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
 107                                  PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
 108
 109         if (mc_dev) {
 110                 unsigned long tomk, tolmk;
 111                 unsigned char rambits;
 112                 int i, idx;
 113
 114                 /*
 115                  * Once the register value is not zero, the RAM size is
 116                  * this register's value multiply 64 * 1024 * 1024.
 117                  */
 118                 for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 119                         rambits = pci_read_config8(mc_dev, ramregs[i]);
 120                         if (rambits != 0)
 121                                 break;
 122                 }
 123
 124                 tomk = rambits * 64 * 1024;
 125                 printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);
 126                 /* Compute the Top Of Low Memory (TOLM), in Kb. */
 127                 tolmk = pci_tolm >> 10;
 128                 if (tolmk >= tomk) {
 129                         /* The PCI hole does does not overlap the memory. */
 130                         tolmk = tomk;
 131                 }
 132
 133                 set_late_cbmem_top((tolmk - CONFIG_VIDEO_MB * 1024) * 1024);
 134
 135                 /* Report the memory regions. */
 136                 idx = 10;
 137                 /* TODO: Hole needed? */
 138                 ram_resource(dev, idx++, 0, 640);       /* First 640k */
 139                 /* Leave a hole for VGA, 0xa0000 - 0xc0000 */
 140                 ram_resource(dev, idx++, 768,
 141                              (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
 142         }
 143         assign_resources(dev->link_list);
 144 }
 145
 146 static struct device_operations pci_domain_ops = {
 147         .read_resources   = pci_domain_read_resources,
 148         .set_resources    = pci_domain_set_resources,
 149         .enable_resources = NULL,
 150         .init             = NULL,
 151         .scan_bus         = pci_domain_scan_bus,
 152 };
 153
 154 static void cpu_bus_init(device_t dev)
 155 {
 156         initialize_cpus(dev->link_list);
 157 }
 158
 159 static struct device_operations cpu_bus_ops = {
 160         .read_resources   = DEVICE_NOOP,
 161         .set_resources    = DEVICE_NOOP,
 162         .enable_resources = DEVICE_NOOP,
 163         .init             = cpu_bus_init,
 164         .scan_bus         = 0,
 165 };
 166
 167 static void enable_dev(struct device *dev)
 168 {
 169         printk(BIOS_SPEW, "In cn700 enable_dev for device %s.\n", dev_path(dev));
 170
 171         /* Set the operations if it is a special bus type. */
 172         if (dev->path.type == DEVICE_PATH_DOMAIN) {
 173                 dev->ops = &pci_domain_ops;
 174         } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
 175                 dev->ops = &cpu_bus_ops;
 176         }
 177 }
 178
 179 struct chip_operations northbridge_via_cn700_ops = {
 180         CHIP_NAME("VIA CN700 Northbridge")
 181         .enable_dev = enable_dev,
 182 };