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{mb,nb,soc}: Remove references to pci_bus_default_ops()
[coreboot.git] / src / northbridge / amd / agesa / family15tn / northbridge.c
blobf47d3122913ee1d38ad5b47783ba665b9f190fa7
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <console/console.h>
18 #include <arch/io.h>
19 #include <arch/acpi.h>
20 #include <arch/acpigen.h>
21 #include <stdint.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <device/hypertransport.h>
26 #include <stdlib.h>
27 #include <string.h>
28 #include <lib.h>
29 #include <cpu/cpu.h>
30 #include <cbmem.h>
31 #include <AGESA.h>
32
33 #include <cpu/x86/lapic.h>
34 #include <cpu/amd/mtrr.h>
35
36 #include <Porting.h>
37 #include <Options.h>
38 #include <Topology.h>
39
40 #include <northbridge/amd/agesa/state_machine.h>
41 #include <northbridge/amd/agesa/agesa_helper.h>
42
43 #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
44
45 typedef struct dram_base_mask {
46 u32 base; //[47:27] at [28:8]
47 u32 mask; //[47:27] at [28:8] and enable at bit 0
48 } dram_base_mask_t;
49
50 static unsigned node_nums;
51 static unsigned sblink;
52 static device_t __f0_dev[MAX_NODE_NUMS];
53 static device_t __f1_dev[MAX_NODE_NUMS];
54 static device_t __f2_dev[MAX_NODE_NUMS];
55 static device_t __f4_dev[MAX_NODE_NUMS];
56 static unsigned fx_devs = 0;
57
58 static dram_base_mask_t get_dram_base_mask(u32 nodeid)
59 {
60 device_t dev;
61 dram_base_mask_t d;
62 dev = __f1_dev[0];
63 u32 temp;
64 temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
65 d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
66 temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
67 d.mask |= temp << 21;
68 temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
69 d.mask |= (temp & 1); // enable bit
70 d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
71 temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
72 d.base |= temp << 21;
73 return d;
74 }
75
76 static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
77 u32 io_min, u32 io_max)
78 {
79 u32 i;
80 u32 tempreg;
81 /* io range allocation */
82 tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
83 for (i = 0; i < node_nums; i++)
84 pci_write_config32(__f1_dev[i], reg+4, tempreg);
85 tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
86 for (i = 0; i < node_nums; i++)
87 pci_write_config32(__f1_dev[i], reg, tempreg);
88 }
89
90 static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
91 {
92 u32 i;
93 u32 tempreg;
94 /* io range allocation */
95 tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
96 for (i = 0; i < nodes; i++)
97 pci_write_config32(__f1_dev[i], reg+4, tempreg);
98 tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
99 for (i = 0; i < node_nums; i++)
100 pci_write_config32(__f1_dev[i], reg, tempreg);
101 }
102
103 static device_t get_node_pci(u32 nodeid, u32 fn)
104 {
105 #if MAX_NODE_NUMS + CONFIG_CDB >= 32
106 if ((CONFIG_CDB + nodeid) < 32) {
107 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
108 } else {
109 return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
110 }
111 #else
112 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
113 #endif
114 }
115
116 static void get_fx_devs(void)
117 {
118 int i;
119 for (i = 0; i < MAX_NODE_NUMS; i++) {
120 __f0_dev[i] = get_node_pci(i, 0);
121 __f1_dev[i] = get_node_pci(i, 1);
122 __f2_dev[i] = get_node_pci(i, 2);
123 __f4_dev[i] = get_node_pci(i, 4);
124 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
125 fx_devs = i+1;
126 }
127 if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
128 die("Cannot find 0:0x18.[0|1]\n");
129 }
130 printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
131 }
132
133 static u32 f1_read_config32(unsigned reg)
134 {
135 if (fx_devs == 0)
136 get_fx_devs();
137 return pci_read_config32(__f1_dev[0], reg);
138 }
139
140 static void f1_write_config32(unsigned reg, u32 value)
141 {
142 int i;
143 if (fx_devs == 0)
144 get_fx_devs();
145 for (i = 0; i < fx_devs; i++) {
146 device_t dev;
147 dev = __f1_dev[i];
148 if (dev && dev->enabled) {
149 pci_write_config32(dev, reg, value);
150 }
151 }
152 }
153
154 static u32 amdfam15_nodeid(struct device *dev)
155 {
156 #if MAX_NODE_NUMS == 64
157 unsigned busn;
158 busn = dev->bus->secondary;
159 if (busn != CONFIG_CBB) {
160 return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
161 } else {
162 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
163 }
164
165 #else
166 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
167 #endif
168 }
169
170 static void set_vga_enable_reg(u32 nodeid, u32 linkn)
171 {
172 u32 val;
173
174 val = 1 | (nodeid << 4) | (linkn << 12);
175 /* it will routing
176 * (1)mmio 0xa0000:0xbffff
177 * (2)io 0x3b0:0x3bb, 0x3c0:0x3df
178 */
179 f1_write_config32(0xf4, val);
180
181 }
182
183 /**
184 * @return
185 * @retval 2 resoure does not exist, usable
186 * @retval 0 resource exists, not usable
187 * @retval 1 resource exist, resource has been allocated before
188 */
189 static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
190 unsigned goal_link)
191 {
192 struct resource *res;
193 unsigned nodeid, link = 0;
194 int result;
195 res = 0;
196 for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
197 struct device *dev;
198 dev = __f0_dev[nodeid];
199 if (!dev)
200 continue;
201 for (link = 0; !res && (link < 8); link++) {
202 res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
203 }
204 }
205 result = 2;
206 if (res) {
207 result = 0;
208 if ((goal_link == (link - 1)) &&
209 (goal_nodeid == (nodeid - 1)) &&
210 (res->flags <= 1)) {
211 result = 1;
212 }
213 }
214 return result;
215 }
216
217 static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
218 {
219 struct resource *resource;
220 u32 free_reg, reg;
221 resource = 0;
222 free_reg = 0;
223 for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
224 int result;
225 result = reg_useable(reg, dev, nodeid, link);
226 if (result == 1) {
227 /* I have been allocated this one */
228 break;
229 }
230 else if (result > 1) {
231 /* I have a free register pair */
232 free_reg = reg;
233 }
234 }
235 if (reg > 0xd8) {
236 reg = free_reg; // if no free, the free_reg still be 0
237 }
238
239 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
240
241 return resource;
242 }
243
244 static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link)
245 {
246 struct resource *resource;
247 u32 free_reg, reg;
248 resource = 0;
249 free_reg = 0;
250 for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
251 int result;
252 result = reg_useable(reg, dev, nodeid, link);
253 if (result == 1) {
254 /* I have been allocated this one */
255 break;
256 }
257 else if (result > 1) {
258 /* I have a free register pair */
259 free_reg = reg;
260 }
261 }
262 if (reg > 0xb8) {
263 reg = free_reg;
264 }
265
266 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
267 return resource;
268 }
269
270 static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link)
271 {
272 struct resource *resource;
273
274 /* Initialize the io space constraints on the current bus */
275 resource = amdfam15_find_iopair(dev, nodeid, link);
276 if (resource) {
277 u32 align;
278 align = log2(HT_IO_HOST_ALIGN);
279 resource->base = 0;
280 resource->size = 0;
281 resource->align = align;
282 resource->gran = align;
283 resource->limit = 0xffffUL;
284 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
285 }
286
287 /* Initialize the prefetchable memory constraints on the current bus */
288 resource = amdfam15_find_mempair(dev, nodeid, link);
289 if (resource) {
290 resource->base = 0;
291 resource->size = 0;
292 resource->align = log2(HT_MEM_HOST_ALIGN);
293 resource->gran = log2(HT_MEM_HOST_ALIGN);
294 resource->limit = 0xffffffffffULL;
295 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
296 resource->flags |= IORESOURCE_BRIDGE;
297 }
298
299 /* Initialize the memory constraints on the current bus */
300 resource = amdfam15_find_mempair(dev, nodeid, link);
301 if (resource) {
302 resource->base = 0;
303 resource->size = 0;
304 resource->align = log2(HT_MEM_HOST_ALIGN);
305 resource->gran = log2(HT_MEM_HOST_ALIGN);
306 resource->limit = 0xffffffffffULL;
307 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
308 }
309
310 }
311
312 static void nb_read_resources(struct device *dev)
313 {
314 u32 nodeid;
315 struct bus *link;
316
317 nodeid = amdfam15_nodeid(dev);
318 for (link = dev->link_list; link; link = link->next) {
319 if (link->children) {
320 amdfam15_link_read_bases(dev, nodeid, link->link_num);
321 }
322 }
323
324 /*
325 * This MMCONF resource must be reserved in the PCI domain.
326 * It is not honored by the coreboot resource allocator if it is in
327 * the CPU_CLUSTER.
328 */
329 mmconf_resource(dev, 0xc0010058);
330 }
331
332 static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
333 {
334 resource_t rbase, rend;
335 unsigned reg, link_num;
336 char buf[50];
337
338 /* Make certain the resource has actually been set */
339 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
340 return;
341 }
342
343 /* If I have already stored this resource don't worry about it */
344 if (resource->flags & IORESOURCE_STORED) {
345 return;
346 }
347
348 /* Only handle PCI memory and IO resources */
349 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
350 return;
351
352 /* Ensure I am actually looking at a resource of function 1 */
353 if ((resource->index & 0xffff) < 0x1000) {
354 return;
355 }
356 /* Get the base address */
357 rbase = resource->base;
358
359 /* Get the limit (rounded up) */
360 rend = resource_end(resource);
361
362 /* Get the register and link */
363 reg = resource->index & 0xfff; // 4k
364 link_num = IOINDEX_LINK(resource->index);
365
366 if (resource->flags & IORESOURCE_IO) {
367 set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
368 }
369 else if (resource->flags & IORESOURCE_MEM) {
370 set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8]
371 }
372 resource->flags |= IORESOURCE_STORED;
373 snprintf(buf, sizeof(buf), " <node %x link %x>",
374 nodeid, link_num);
375 report_resource_stored(dev, resource, buf);
376 }
377
378 /**
379 * I tried to reuse the resource allocation code in set_resource()
380 * but it is too difficult to deal with the resource allocation magic.
381 */
382
383 static void create_vga_resource(struct device *dev, unsigned nodeid)
384 {
385 struct bus *link;
386
387 /* find out which link the VGA card is connected,
388 * we only deal with the 'first' vga card */
389 for (link = dev->link_list; link; link = link->next) {
390 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
391 #if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
392 extern struct device *vga_pri; // the primary vga device, defined in device.c
393 printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
394 link->secondary,link->subordinate);
395 /* We need to make sure the vga_pri is under the link */
396 if ((vga_pri->bus->secondary >= link->secondary) &&
397 (vga_pri->bus->secondary <= link->subordinate))
398 #endif
399 break;
400 }
401 }
402
403 /* no VGA card installed */
404 if (link == NULL)
405 return;
406
407 printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink);
408 set_vga_enable_reg(nodeid, sblink);
409 }
410
411 static void nb_set_resources(struct device *dev)
412 {
413 unsigned nodeid;
414 struct bus *bus;
415 struct resource *res;
416
417 /* Find the nodeid */
418 nodeid = amdfam15_nodeid(dev);
419
420 create_vga_resource(dev, nodeid); //TODO: do we need this?
421
422 /* Set each resource we have found */
423 for (res = dev->resource_list; res; res = res->next) {
424 set_resource(dev, res, nodeid);
425 }
426
427 for (bus = dev->link_list; bus; bus = bus->next) {
428 if (bus->children) {
429 assign_resources(bus);
430 }
431 }
432 }
433
434 static unsigned long acpi_fill_hest(acpi_hest_t *hest)
435 {
436 void *addr, *current;
437
438 /* Skip the HEST header. */
439 current = (void *)(hest + 1);
440
441 addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
442 if (addr != NULL)
443 current += acpi_create_hest_error_source(hest, current, 0,
444 addr + 2, *(UINT16 *)addr - 2);
445
446 addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
447 if (addr != NULL)
448 current += acpi_create_hest_error_source(hest, current, 1,
449 addr + 2, *(UINT16 *)addr - 2);
450
451 return (unsigned long)current;
452 }
453
454 static void northbridge_fill_ssdt_generator(device_t device)
455 {
456 msr_t msr;
457 char pscope[] = "\\_SB.PCI0";
458
459 acpigen_write_scope(pscope);
460 msr = rdmsr(TOP_MEM);
461 acpigen_write_name_dword("TOM1", msr.lo);
462 msr = rdmsr(TOP_MEM2);
463 /*
464 * Since XP only implements parts of ACPI 2.0, we can't use a qword
465 * here.
466 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
467 * slide 22ff.
468 * Shift value right by 20 bit to make it fit into 32bit,
469 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
470 */
471 acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
472 acpigen_pop_len();
473 }
474
475 static unsigned long agesa_write_acpi_tables(device_t device,
476 unsigned long current,
477 acpi_rsdp_t *rsdp)
478 {
479 acpi_srat_t *srat;
480 acpi_slit_t *slit;
481 acpi_header_t *ssdt;
482 acpi_header_t *alib;
483 acpi_header_t *ivrs;
484 acpi_hest_t *hest;
485
486 /* HEST */
487 current = ALIGN(current, 8);
488 hest = (acpi_hest_t *)current;
489 acpi_write_hest((void *)current, acpi_fill_hest);
490 acpi_add_table(rsdp, (void *)current);
491 current += ((acpi_header_t *)current)->length;
492
493 current = ALIGN(current, 8);
494 printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
495 ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
496 if (ivrs != NULL) {
497 memcpy((void *)current, ivrs, ivrs->length);
498 ivrs = (acpi_header_t *) current;
499 current += ivrs->length;
500 acpi_add_table(rsdp, ivrs);
501 } else {
502 printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
503 }
504
505 /* SRAT */
506 current = ALIGN(current, 8);
507 printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
508 srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
509 if (srat != NULL) {
510 memcpy((void *)current, srat, srat->header.length);
511 srat = (acpi_srat_t *) current;
512 current += srat->header.length;
513 acpi_add_table(rsdp, srat);
514 } else {
515 printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
516 }
517
518 /* SLIT */
519 current = ALIGN(current, 8);
520 printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
521 slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
522 if (slit != NULL) {
523 memcpy((void *)current, slit, slit->header.length);
524 slit = (acpi_slit_t *) current;
525 current += slit->header.length;
526 acpi_add_table(rsdp, slit);
527 } else {
528 printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
529 }
530
531 /* ALIB */
532 current = ALIGN(current, 16);
533 printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
534 alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
535 if (alib != NULL) {
536 memcpy((void *)current, alib, alib->length);
537 alib = (acpi_header_t *) current;
538 current += alib->length;
539 acpi_add_table(rsdp, (void *)alib);
540 }
541 else {
542 printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
543 }
544
545 /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */
546 /* SSDT */
547 current = ALIGN(current, 16);
548 printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
549 ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
550 if (ssdt != NULL) {
551 memcpy((void *)current, ssdt, ssdt->length);
552 ssdt = (acpi_header_t *) current;
553 current += ssdt->length;
554 }
555 else {
556 printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
557 }
558 acpi_add_table(rsdp,ssdt);
559
560 printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
561
562 return current;
563 }
564
565
566 static struct device_operations northbridge_operations = {
567 .read_resources = nb_read_resources,
568 .set_resources = nb_set_resources,
569 .enable_resources = pci_dev_enable_resources,
570 .init = DEVICE_NOOP,
571 .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator,
572 .write_acpi_tables = agesa_write_acpi_tables,
573 .enable = 0,
574 .ops_pci = 0,
575 };
576
577 static const struct pci_driver family15_northbridge __pci_driver = {
578 .ops = &northbridge_operations,
579 .vendor = PCI_VENDOR_ID_AMD,
580 .device = PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT,
581 };
582
583 static const struct pci_driver family10_northbridge __pci_driver = {
584 .ops = &northbridge_operations,
585 .vendor = PCI_VENDOR_ID_AMD,
586 .device = PCI_DEVICE_ID_AMD_10H_NB_HT,
587 };
588
589 struct chip_operations northbridge_amd_agesa_family15tn_ops = {
590 CHIP_NAME("AMD FAM15 Northbridge")
591 .enable_dev = 0,
592 };
593
594 static void domain_read_resources(struct device *dev)
595 {
596 unsigned reg;
597
598 /* Find the already assigned resource pairs */
599 get_fx_devs();
600 for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
601 u32 base, limit;
602 base = f1_read_config32(reg);
603 limit = f1_read_config32(reg + 0x04);
604 /* Is this register allocated? */
605 if ((base & 3) != 0) {
606 unsigned nodeid, reg_link;
607 device_t reg_dev;
608 if (reg < 0xc0) { // mmio
609 nodeid = (limit & 0xf) + (base&0x30);
610 } else { // io
611 nodeid = (limit & 0xf) + ((base>>4)&0x30);
612 }
613 reg_link = (limit >> 4) & 7;
614 reg_dev = __f0_dev[nodeid];
615 if (reg_dev) {
616 /* Reserve the resource */
617 struct resource *res;
618 res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
619 if (res) {
620 res->flags = 1;
621 }
622 }
623 }
624 }
625 /* FIXME: do we need to check extend conf space?
626 I don't believe that much preset value */
627
628 pci_domain_read_resources(dev);
629 }
630
631 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
632 struct hw_mem_hole_info {
633 unsigned hole_startk;
634 int node_id;
635 };
636 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
637 {
638 struct hw_mem_hole_info mem_hole;
639 int i;
640 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
641 mem_hole.node_id = -1;
642 for (i = 0; i < node_nums; i++) {
643 dram_base_mask_t d;
644 u32 hole;
645 d = get_dram_base_mask(i);
646 if (!(d.mask & 1)) continue; // no memory on this node
647 hole = pci_read_config32(__f1_dev[i], 0xf0);
648 if (hole & 1) { // we find the hole
649 mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
650 mem_hole.node_id = i; // record the node No with hole
651 break; // only one hole
652 }
653 }
654
655 /* We need to double check if there is special set on base reg and limit reg
656 * are not continuous instead of hole, it will find out its hole_startk.
657 */
658 if (mem_hole.node_id == -1) {
659 resource_t limitk_pri = 0;
660 for (i = 0; i < node_nums; i++) {
661 dram_base_mask_t d;
662 resource_t base_k, limit_k;
663 d = get_dram_base_mask(i);
664 if (!(d.base & 1)) continue;
665 base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
666 if (base_k > 4 *1024 * 1024) break; // don't need to go to check
667 if (limitk_pri != base_k) { // we find the hole
668 mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
669 mem_hole.node_id = i;
670 break; //only one hole
671 }
672 limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
673 limitk_pri = limit_k;
674 }
675 }
676 return mem_hole;
677 }
678 #endif
679
680 static void domain_set_resources(struct device *dev)
681 {
682 unsigned long mmio_basek;
683 u32 pci_tolm;
684 int i, idx;
685 struct bus *link;
686 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
687 struct hw_mem_hole_info mem_hole;
688 u32 reset_memhole = 1;
689 #endif
690
691 pci_tolm = 0xffffffffUL;
692 for (link = dev->link_list; link; link = link->next) {
693 pci_tolm = find_pci_tolm(link);
694 }
695
696 // FIXME handle interleaved nodes. If you fix this here, please fix
697 // amdk8, too.
698 mmio_basek = pci_tolm >> 10;
699 /* Round mmio_basek to something the processor can support */
700 mmio_basek &= ~((1 << 6) -1);
701
702 // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
703 // MMIO hole. If you fix this here, please fix amdk8, too.
704 /* Round the mmio hole to 64M */
705 mmio_basek &= ~((64*1024) - 1);
706
707 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
708 /* if the hw mem hole is already set in raminit stage, here we will compare
709 * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
710 * use hole_basek as mmio_basek and we don't need to reset hole.
711 * otherwise We reset the hole to the mmio_basek
712 */
713
714 mem_hole = get_hw_mem_hole_info();
715
716 // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
717 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
718 mmio_basek = mem_hole.hole_startk;
719 reset_memhole = 0;
720 }
721 #endif
722
723 idx = 0x10;
724 for (i = 0; i < node_nums; i++) {
725 dram_base_mask_t d;
726 resource_t basek, limitk, sizek; // 4 1T
727
728 d = get_dram_base_mask(i);
729
730 if (!(d.mask & 1)) continue;
731 basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
732 limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
733
734 sizek = limitk - basek;
735
736 /* see if we need a hole from 0xa0000 to 0xbffff */
737 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
738 ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
739 idx += 0x10;
740 basek = (8*64)+(16*16);
741 sizek = limitk - ((8*64)+(16*16));
742
743 }
744
745 /* split the region to accommodate pci memory space */
746 if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
747 if (basek <= mmio_basek) {
748 unsigned pre_sizek;
749 pre_sizek = mmio_basek - basek;
750 if (pre_sizek > 0) {
751 ram_resource(dev, (idx | i), basek, pre_sizek);
752 idx += 0x10;
753 sizek -= pre_sizek;
754 }
755 basek = mmio_basek;
756 }
757 if ((basek + sizek) <= 4*1024*1024) {
758 sizek = 0;
759 }
760 else {
761 uint64_t topmem2 = bsp_topmem2();
762 basek = 4*1024*1024;
763 sizek = topmem2/1024 - basek;
764 }
765 }
766
767 ram_resource(dev, (idx | i), basek, sizek);
768 idx += 0x10;
769 printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
770 i, mmio_basek, basek, limitk);
771 }
772
773 add_uma_resource_below_tolm(dev, 7);
774
775 for (link = dev->link_list; link; link = link->next) {
776 if (link->children) {
777 assign_resources(link);
778 }
779 }
780 }
781
782 static struct device_operations pci_domain_ops = {
783 .read_resources = domain_read_resources,
784 .set_resources = domain_set_resources,
785 .init = DEVICE_NOOP,
786 .scan_bus = pci_domain_scan_bus,
787 };
788
789 static void sysconf_init(device_t dev) // first node
790 {
791 sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
792 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
793 }
794
795 static void add_more_links(struct device *dev, unsigned total_links)
796 {
797 struct bus *link, *last = NULL;
798 int link_num;
799
800 for (link = dev->link_list; link; link = link->next)
801 last = link;
802
803 if (last) {
804 int links = total_links - last->link_num;
805 link_num = last->link_num;
806 if (links > 0) {
807 link = malloc(links*sizeof(*link));
808 if (!link)
809 die("Couldn't allocate more links!\n");
810 memset(link, 0, links*sizeof(*link));
811 last->next = link;
812 }
813 }
814 else {
815 link_num = -1;
816 link = malloc(total_links*sizeof(*link));
817 memset(link, 0, total_links*sizeof(*link));
818 dev->link_list = link;
819 }
820
821 for (link_num = link_num + 1; link_num < total_links; link_num++) {
822 link->link_num = link_num;
823 link->dev = dev;
824 link->next = link + 1;
825 last = link;
826 link = link->next;
827 }
828 last->next = NULL;
829 }
830
831 static void cpu_bus_scan(device_t dev)
832 {
833 struct bus *cpu_bus;
834 device_t dev_mc;
835 #if CONFIG_CBB
836 device_t pci_domain;
837 #endif
838 int i,j;
839 int coreid_bits;
840 int core_max = 0;
841 unsigned ApicIdCoreIdSize;
842 unsigned core_nums;
843 int siblings = 0;
844 unsigned int family;
845
846 #if CONFIG_CBB
847 dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
848 if (dev_mc && dev_mc->bus) {
849 printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
850 pci_domain = dev_mc->bus->dev;
851 if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
852 printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
853 dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
854 printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
855 } else {
856 printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
857 }
858 printk(BIOS_DEBUG, "\n");
859 }
860 dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
861 if (!dev_mc) {
862 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
863 if (dev_mc && dev_mc->bus) {
864 printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
865 pci_domain = dev_mc->bus->dev;
866 if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
867 if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
868 printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
869 dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
870 printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
871 while (dev_mc) {
872 printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
873 dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
874 printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
875 dev_mc = dev_mc->sibling;
876 }
877 }
878 }
879 }
880 }
881 #endif
882 dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
883 if (!dev_mc) {
884 printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
885 die("");
886 }
887 sysconf_init(dev_mc);
888 #if CONFIG_CBB && (MAX_NODE_NUMS > 32)
889 if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe
890 if (pci_domain->link_list && !pci_domain->link_list->next) {
891 struct bus *new_link = new_link(pci_domain);
892 pci_domain->link_list->next = new_link;
893 new_link->link_num = 1;
894 new_link->dev = pci_domain;
895 new_link->children = 0;
896 printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain));
897 }
898 pci_domain->link_list->next->secondary = CONFIG_CBB - 1;
899 }
900 #endif
901
902 /* Get Max Number of cores(MNC) */
903 coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
904 core_max = 1 << (coreid_bits & 0x000F); //mnc
905
906 ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
907 if (ApicIdCoreIdSize) {
908 core_nums = (1 << ApicIdCoreIdSize) - 1;
909 } else {
910 core_nums = 3; //quad core
911 }
912
913 /* Find which cpus are present */
914 cpu_bus = dev->link_list;
915 for (i = 0; i < node_nums; i++) {
916 device_t cdb_dev;
917 unsigned busn, devn;
918 struct bus *pbus;
919
920 busn = CONFIG_CBB;
921 devn = CONFIG_CDB + i;
922 pbus = dev_mc->bus;
923 #if CONFIG_CBB && (MAX_NODE_NUMS > 32)
924 if (i >= 32) {
925 busn--;
926 devn -= 32;
927 pbus = pci_domain->link_list->next;
928 }
929 #endif
930
931 /* Find the cpu's pci device */
932 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
933 if (!cdb_dev) {
934 /* If I am probing things in a weird order
935 * ensure all of the cpu's pci devices are found.
936 */
937 int fn;
938 for (fn = 0; fn <= 5; fn++) { //FBDIMM?
939 cdb_dev = pci_probe_dev(NULL, pbus,
940 PCI_DEVFN(devn, fn));
941 }
942 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
943 } else {
944 /* Ok, We need to set the links for that device.
945 * otherwise the device under it will not be scanned
946 */
947 add_more_links(cdb_dev, 4);
948 }
949
950 family = cpuid_eax(1);
951 family = (family >> 20) & 0xFF;
952 if (family == 1) { //f10
953 u32 dword;
954 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
955 dword = pci_read_config32(cdb_dev, 0xe8);
956 siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
957 } else if (family == 6) {//f15
958 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5));
959 if (cdb_dev && cdb_dev->enabled) {
960 siblings = pci_read_config32(cdb_dev, 0x84);
961 siblings &= 0xFF;
962 }
963 } else {
964 siblings = 0; //default one core
965 }
966 int enable_node = cdb_dev && cdb_dev->enabled;
967 printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
968 dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
969
970 for (j = 0; j <= siblings; j++) {
971 extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
972 u32 modules = TopologyConfiguration.PlatformNumberOfModules;
973 u32 lapicid_start = 0;
974
975 /*
976 * APIC ID calucation is tightly coupled with AGESA v5 code.
977 * This calculation MUST match the assignment calculation done
978 * in LocalApicInitializationAtEarly() function.
979 * And reference GetLocalApicIdForCore()
980 *
981 * Apply apic enumeration rules
982 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
983 * put the local-APICs at m..z
984 *
985 * This is needed because many IO-APIC devices only have 4 bits
986 * for their APIC id and therefore must reside at 0..15
987 */
988
989 u8 plat_num_io_apics = 3; /* FIXME */
990
991 if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
992 lapicid_start = (plat_num_io_apics - 1) / core_max;
993 lapicid_start = (lapicid_start + 1) * core_max;
994 printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
995 }
996 u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
997 printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
998 i, j, apic_id);
999
1000 device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
1001 if (cpu)
1002 amd_cpu_topology(cpu, i, j);
1003 } //j
1004 }
1005 }
1006
1007 static void cpu_bus_init(struct device *dev)
1008 {
1009 initialize_cpus(dev->link_list);
1010 }
1011
1012 static struct device_operations cpu_bus_ops = {
1013 .read_resources = DEVICE_NOOP,
1014 .set_resources = DEVICE_NOOP,
1015 .enable_resources = DEVICE_NOOP,
1016 .init = cpu_bus_init,
1017 .scan_bus = cpu_bus_scan,
1018 };
1019
1020 static void root_complex_enable_dev(struct device *dev)
1021 {
1022 static int done = 0;
1023
1024 if (!done) {
1025 setup_bsp_ramtop();
1026 done = 1;
1027 }
1028
1029 /* Set the operations if it is a special bus type */
1030 if (dev->path.type == DEVICE_PATH_DOMAIN) {
1031 dev->ops = &pci_domain_ops;
1032 } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
1033 dev->ops = &cpu_bus_ops;
1034 }
1035 }
1036
1037 struct chip_operations northbridge_amd_agesa_family15tn_root_complex_ops = {
1038 CHIP_NAME("AMD Family 15tn Root Complex")
1039 .enable_dev = root_complex_enable_dev,
1040 };
1041
1042 /*********************************************************************
1043 * Change the vendor / device IDs to match the generic VBIOS header. *
1044 *********************************************************************/
1045 u32 map_oprom_vendev(u32 vendev)
1046 {
1047 u32 new_vendev = vendev;
1048
1049 switch(vendev) {
1050 case 0x10029900: /* AMD Radeon HD 7660G (Trinity) */
1051 case 0x10029901: /* AMD Radeon HD 7660D (Trinity) */
1052 case 0x10029903: /* AMD Radeon HD 7640G (Trinity) */
1053 case 0x10029904: /* AMD Radeon HD 7560D (Trinity) */
1054 case 0x10029907: /* AMD Radeon HD 7620G (Trinity) */
1055 case 0x10029908: /* AMD Radeon HD 7600G (Trinity) */
1056 case 0x1002990A: /* AMD Radeon HD 7500G (Trinity) */
1057 case 0x1002990B: /* AMD Radeon HD 8650G (Richland) */
1058 case 0x1002990C: /* AMD Radeon HD 8670D (Richland) */
1059 case 0x1002990D: /* AMD Radeon HD 8550G (Richland) */
1060 case 0x1002990E: /* AMD Radeon HD 8570D (Richland) */
1061 case 0x1002990F: /* AMD Radeon HD 8610G (Richland) */
1062 case 0x10029910: /* AMD Radeon HD 7660G (Trinity) */
1063 case 0x10029913: /* AMD Radeon HD 7640G (Trinity) */
1064 case 0x10029917: /* AMD Radeon HD 7620G (Trinity) */
1065 case 0x10029918: /* AMD Radeon HD 7600G (Trinity) */
1066 case 0x10029919: /* AMD Radeon HD 7500G (Trinity) */
1067 case 0x10029990: /* AMD Radeon HD 7520G (Trinity) */
1068 case 0x10029991: /* AMD Radeon HD 7540D (Trinity) */
1069 case 0x10029992: /* AMD Radeon HD 7420G (Trinity) */
1070 case 0x10029993: /* AMD Radeon HD 7480D (Trinity) */
1071 case 0x10029994: /* AMD Radeon HD 7400G (Trinity) */
1072 case 0x10029995: /* AMD Radeon HD 8450G (Richland) */
1073 case 0x10029996: /* AMD Radeon HD 8470D (Richland) */
1074 case 0x10029997: /* AMD Radeon HD 8350G (Richland) */
1075 case 0x10029998: /* AMD Radeon HD 8370D (Richland) */
1076 case 0x10029999: /* AMD Radeon HD 8510G (Richland) */
1077 case 0x1002999A: /* AMD Radeon HD 8410G (Richland) */
1078 case 0x1002999B: /* AMD Radeon HD 8310G (Richland) */
1079 case 0x1002999C: /* AMD Radeon HD 8650D (Richland) */
1080 case 0x1002999D: /* AMD Radeon HD 8550D (Richland) */
1081 case 0x100299A0: /* AMD Radeon HD 7520G (Trinity) */
1082 case 0x100299A2: /* AMD Radeon HD 7420G (Trinity) */
1083 case 0x100299A4: /* AMD Radeon HD 7400G (Trinity) */
1084 new_vendev = 0x10029901;
1085 break;
1086 }
1087
1088 return new_vendev;
1089 }
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