1 ## SPDX-License-Identifier: GPL-2.0-only
3 mainmenu "coreboot configuration"
12 string "Local version string"
14 Append an extra string to the end of the coreboot version.
16 This can be useful if, for instance, you want to append the
17 respective board's hostname or some other identifying string to
18 the coreboot version number, so that you can easily distinguish
19 boot logs of different boards from each other.
21 config CONFIGURABLE_CBFS_PREFIX
24 Select this to prompt to use to configure the prefix for cbfs files.
27 prompt "CBFS prefix to use"
28 depends on CONFIGURABLE_CBFS_PREFIX
29 default CBFS_PREFIX_FALLBACK
31 config CBFS_PREFIX_FALLBACK
34 config CBFS_PREFIX_NORMAL
37 config CBFS_PREFIX_DIY
38 bool "Define your own cbfs prefix"
43 string "CBFS prefix to use" if CBFS_PREFIX_DIY
44 default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
45 default "normal" if CBFS_PREFIX_NORMAL
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
51 prompt "Compiler to use"
54 This option allows you to select the compiler used for building
56 You must build the coreboot crosscompiler for the board that you
59 To build all the GCC crosscompilers (takes a LONG time), run:
62 For help on individual architectures, run the command:
68 Use the GNU Compiler Collection (GCC) to build coreboot.
70 For details see http://gcc.gnu.org.
72 config COMPILER_LLVM_CLANG
73 bool "LLVM/clang (TESTING ONLY - Not currently working)"
75 Use LLVM/clang to build coreboot. To use this, you must build the
76 coreboot version of the clang compiler. Run the command
78 Note that this option is not currently working correctly and should
79 really only be selected if you're trying to work on getting clang
82 For details see http://clang.llvm.org.
87 bool "Allow building with any toolchain"
90 Many toolchains break when building coreboot since it uses quite
91 unusual linker features. Unless developers explicitely request it,
92 we'll have to assume that they use their distro compiler by mistake.
93 Make sure that using patched compilers is a conscious decision.
96 bool "Use ccache to speed up (re)compilation"
99 Enables the use of ccache for faster builds.
101 Requires the ccache utility in your system $PATH.
103 For details see https://ccache.samba.org.
106 bool "Generate flashmap descriptor parser using flex and bison"
109 Enable this option if you are working on the flashmap descriptor
110 parser and made changes to fmd_scanner.l or fmd_parser.y.
112 Otherwise, say N to use the provided pregenerated scanner/parser.
114 config UTIL_GENPARSER
115 bool "Generate parsers for bincfg, sconfig and kconfig locally"
118 Enable this option if you are working on the sconfig device tree
119 parser or bincfg and made changes to the .l or .y files.
121 Otherwise, say N to use the provided pregenerated scanner/parser.
124 prompt "Option backend to use"
125 default USE_MAINBOARD_SPECIFIC_OPTION_BACKEND if HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
126 default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD
128 config OPTION_BACKEND_NONE
131 config USE_OPTION_TABLE
132 bool "Use CMOS for configuration values"
133 depends on HAVE_OPTION_TABLE
135 Enable this option if coreboot shall read options from the "CMOS"
136 NVRAM instead of using hard-coded values.
138 config USE_MAINBOARD_SPECIFIC_OPTION_BACKEND
139 bool "Use mainboard-specific option backend"
140 depends on HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
142 Use a mainboard-specific mechanism to access runtime-configurable
147 config STATIC_OPTION_TABLE
148 bool "Load default configuration values into CMOS on each boot"
149 depends on USE_OPTION_TABLE
151 Enable this option to reset "CMOS" NVRAM values to default on
152 every boot. Use this if you want the NVRAM configuration to
153 never be modified from its default values.
155 config COMPRESS_RAMSTAGE
156 bool "Compress ramstage with LZMA"
157 depends on HAVE_RAMSTAGE
158 # Default value set at the end of the file
160 Compress ramstage to save memory in the flash image.
162 config COMPRESS_PRERAM_STAGES
163 bool "Compress romstage and verstage with LZ4"
164 depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
165 # Default value set at the end of the file
167 Compress romstage and (if it exists) verstage with LZ4 to save flash
168 space and speed up boot, since the time for reading the image from SPI
169 (and in the vboot case verifying it) is usually much greater than the
170 time spent decompressing. Doesn't work for XIP stages (assume all
171 ARCH_X86 for now) for obvious reasons.
173 config COMPRESS_BOOTBLOCK
175 depends on HAVE_BOOTBLOCK
177 This option can be used to compress the bootblock with LZ4 and attach
178 a small self-decompression stub to its front. This can drastically
179 reduce boot time on platforms where the bootblock is loaded over a
180 very slow connection and bootblock size trumps all other factors for
181 speed. Since using this option usually requires changes to the
182 SoC memlayout and possibly extra support code, it should not be
183 user-selectable. (There's no real point in offering this to the user
184 anyway... if it works and saves boot time, you would always want it.)
186 config INCLUDE_CONFIG_FILE
187 bool "Include the coreboot .config file into the ROM image"
188 # Default value set at the end of the file
190 Include the .config file that was used to compile coreboot
191 in the (CBFS) ROM image. This is useful if you want to know which
192 options were used to build a specific coreboot.rom image.
194 Saying Y here will increase the image size by 2-3KB.
196 You can use the following command to easily list the options:
198 grep -a CONFIG_ coreboot.rom
200 Alternatively, you can also use cbfstool to print the image
201 contents (including the raw 'config' item we're looking for).
205 $ cbfstool coreboot.rom print
206 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
210 Name Offset Type Size
211 cmos_layout.bin 0x0 CMOS layout 1159
212 fallback/romstage 0x4c0 stage 339756
213 fallback/ramstage 0x53440 stage 186664
214 fallback/payload 0x80dc0 payload 51526
215 config 0x8d740 raw 3324
216 (empty) 0x8e480 null 3610440
218 config COLLECT_TIMESTAMPS
219 bool "Create a table of timestamps collected during boot"
220 default y if ARCH_X86
222 Make coreboot create a table of timer-ID/timer-value pairs to
223 allow measuring time spent at different phases of the boot process.
225 config TIMESTAMPS_ON_CONSOLE
226 bool "Print the timestamp values on the console"
228 depends on COLLECT_TIMESTAMPS
230 Print the timestamps to the debug console if enabled at level info.
233 bool "Allow use of binary-only repository"
236 This draws in the blobs repository, which contains binary files that
237 might be required for some chipsets or boards.
238 This flag ensures that a "Free" option remains available for users.
241 bool "Allow AMD blobs repository (with license agreement)"
244 This draws in the amd_blobs repository, which contains binary files
245 distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares,
246 etc. Selecting this item to download or clone the repo implies your
247 agreement to the AMD license agreement. A copy of the license text
248 may be reviewed by reading Documentation/soc/amd/amdblobs_license.md,
249 and your copy of the license is present in the repo once downloaded.
251 Note that for some products, omitting PSP, SMU images, or other items
252 may result in a nonbooting coreboot.rom.
255 bool "Allow QC blobs repository (selecting this agrees to the license!)"
258 This draws in the qc_blobs repository, which contains binary files
259 distributed by Qualcomm that are required to build firmware for
260 certain Qualcomm SoCs (including QcLib, QC-SEC, qtiseclib and QUP
261 firmware). If you say Y here you are implicitly agreeing to the
262 Qualcomm license agreement which can be found at:
263 https://review.coreboot.org/cgit/qc_blobs.git/tree/LICENSE
265 *****************************************************
266 PLEASE MAKE SURE YOU READ AND AGREE TO ALL TERMS IN
267 ABOVE LICENSE AGREEMENT BEFORE SELECTING THIS OPTION!
268 *****************************************************
270 Not selecting this option means certain Qualcomm SoCs and related
271 mainboards cannot be built and will be hidden from the "Mainboards"
275 bool "Code coverage support"
276 depends on COMPILER_GCC
278 Add code coverage support for coreboot. This will store code
279 coverage information in CBMEM for extraction from user space.
283 bool "Undefined behavior sanitizer support"
286 Instrument the code with checks for undefined behavior. If unsure,
287 say N because it adds a small performance penalty and may abort
288 on code that happens to work in spite of the UB.
290 config HAVE_ASAN_IN_ROMSTAGE
294 config ASAN_IN_ROMSTAGE
298 Enable address sanitizer in romstage for platform.
300 config HAVE_ASAN_IN_RAMSTAGE
304 config ASAN_IN_RAMSTAGE
308 Enable address sanitizer in ramstage for platform.
311 bool "Address sanitizer support"
313 select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE
314 select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE
316 Enable address sanitizer - runtime memory debugger,
317 designed to find out-of-bounds accesses and use-after-scope bugs.
319 This feature consumes up to 1/8 of available memory and brings about
320 ~1.5x performance slowdown.
325 comment "Before using this feature, make sure that "
326 comment "asan_shadow_offset_callback patch is applied to GCC."
330 prompt "Stage Cache for ACPI S3 resume"
331 default NO_STAGE_CACHE if !HAVE_ACPI_RESUME
332 default TSEG_STAGE_CACHE if SMM_TSEG
334 config NO_STAGE_CACHE
337 Do not save any component in stage cache for resume path. On resume,
338 all components would be read back from CBFS again.
340 config TSEG_STAGE_CACHE
344 The option enables stage cache support for platform. Platform
345 can stash copies of postcar, ramstage and raw runtime data
346 inside SMM TSEG, to be restored on S3 resume path.
348 config CBMEM_STAGE_CACHE
352 The option enables stage cache support for platform. Platform
353 can stash copies of postcar, ramstage and raw runtime data
356 While the approach is faster than reloading stages from boot media
357 it is also a possible attack scenario via which OS can possibly
358 circumvent SMM locks and SPI write protections.
360 If unsure, select 'N'
365 bool "Update existing coreboot.rom image"
367 If this option is enabled, no new coreboot.rom file
368 is created. Instead it is expected that there already
369 is a suitable file for further processing.
370 The bootblock will not be modified.
372 If unsure, select 'N'
374 config BOOTSPLASH_IMAGE
375 bool "Add a bootsplash image"
377 Select this option if you have a bootsplash image that you would
378 like to add to your ROM.
380 This will only add the image to the ROM. To actually run it check
381 options under 'Display' section.
383 config BOOTSPLASH_FILE
384 string "Bootsplash path and filename"
385 depends on BOOTSPLASH_IMAGE
386 # Default value set at the end of the file
388 The path and filename of the file to use as graphical bootsplash
389 screen. The file format has to be jpg.
392 bool "Firmware Configuration Probing"
395 Enable support for probing devices with fw_config. This is a simple
396 bitmask broken into fields and options for probing.
398 config FW_CONFIG_SOURCE_CHROMEEC_CBI
399 bool "Obtain Firmware Configuration value from Google Chrome EC CBI"
400 depends on FW_CONFIG && EC_GOOGLE_CHROMEEC
403 This option tells coreboot to read the firmware configuration value
404 from the Google Chrome Embedded Controller CBI interface. This source
405 is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was
408 config FW_CONFIG_SOURCE_CBFS
409 bool "Obtain Firmware Configuration value from CBFS"
413 With this option enabled coreboot will look for the 32bit firmware
414 configuration value in CBFS at the selected prefix with the file name
415 "fw_config". This option will override other sources and allow the
416 local image to preempt the mainboard selected source and can be used as
417 FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option.
419 config FW_CONFIG_SOURCE_VPD
420 bool "Obtain Firmware Configuration value from VPD"
421 depends on FW_CONFIG && VPD
424 With this option enabled coreboot will look for the 32bit firmware
425 configuration value in VPD key name "fw_config". This option will
426 override other sources and allow the local image to preempt the mainboard
427 selected source and can be used for other FW_CONFIG_SOURCEs fallback option.
429 config HAVE_RAMPAYLOAD
433 bool "Enable coreboot flow without executing ramstage"
434 default y if ARCH_X86
435 depends on HAVE_RAMPAYLOAD
437 If this option is enabled, coreboot flow will skip ramstage
438 loading and execution of ramstage to load payload.
440 Instead it is expected to load payload from postcar stage itself.
442 In this flow coreboot will perform basic x86 initialization
443 (DRAM resource allocation), MTRR programming,
444 Skip PCI enumeration logic and only allocate BAR for fixed devices
445 (bootable devices, TPM over GSPI).
447 config HAVE_CONFIGURABLE_RAMSTAGE
450 config CONFIGURABLE_RAMSTAGE
451 bool "Enable a configurable ramstage."
452 default y if ARCH_X86
453 depends on HAVE_CONFIGURABLE_RAMSTAGE
455 A configurable ramstage allows you to select which parts of the ramstage
456 to run. Currently, we can only select a minimal PCI scanning step.
457 The minimal PCI scanning will only check those parts that are enabled
458 in the devicetree.cb. By convention none of those devices should be bridges.
460 config MINIMAL_PCI_SCANNING
461 bool "Enable minimal PCI scanning"
462 depends on CONFIGURABLE_RAMSTAGE && PCI
464 If this option is enabled, coreboot will scan only PCI devices
465 marked as mandatory in devicetree.cb
470 source "src/mainboard/Kconfig"
474 default "devicetree.cb"
476 This symbol allows mainboards to select a different file under their
477 mainboard directory for the devicetree.cb file. This allows the board
478 variants that need different devicetrees to be in the same directory.
480 Examples: "devicetree.variant.cb"
481 "variant/devicetree.cb"
483 config OVERRIDE_DEVICETREE
487 This symbol allows variants to provide an override devicetree file to
488 override the registers and/or add new devices on top of the ones
489 provided by baseboard devicetree using CONFIG_DEVICETREE.
491 Examples: "devicetree.variant-override.cb"
492 "variant/devicetree-override.cb"
495 string "fmap description file in fmd format"
496 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
499 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
500 but in some cases more complex setups are required.
501 When an fmd is specified, it overrides the default format.
504 hex "Size of CBFS filesystem in ROM"
505 depends on FMDFILE = ""
506 # Default value set at the end of the file
508 This is the part of the ROM actually managed by CBFS, located at the
509 end of the ROM (passed through cbfstool -o) on x86 and at at the start
510 of the ROM (passed through cbfstool -s) everywhere else. It defaults
511 to span the whole ROM on all but Intel systems that use an Intel Firmware
512 Descriptor. It can be overridden to make coreboot live alongside other
513 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
514 binaries. This symbol should only be used to generate a default FMAP and
515 is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
519 # load site-local kconfig to allow user specific defaults and overrides
520 source "site-local/Kconfig"
522 config SYSTEM_TYPE_LAPTOP
526 config SYSTEM_TYPE_TABLET
530 config SYSTEM_TYPE_DETACHABLE
534 config SYSTEM_TYPE_CONVERTIBLE
538 config CBFS_AUTOGEN_ATTRIBUTES
542 If this option is selected, every file in cbfs which has a constraint
543 regarding position or alignment will get an additional file attribute
544 which describes this constraint.
549 source "src/soc/*/Kconfig"
551 source "src/cpu/Kconfig"
552 comment "Northbridge"
553 source "src/northbridge/*/*/Kconfig"
554 source "src/northbridge/*/*/Kconfig.common"
555 comment "Southbridge"
556 source "src/southbridge/*/*/Kconfig"
557 source "src/southbridge/*/*/Kconfig.common"
559 source "src/superio/*/*/Kconfig"
560 comment "Embedded Controllers"
561 source "src/ec/acpi/Kconfig"
562 source "src/ec/*/*/Kconfig"
564 source "src/southbridge/intel/common/firmware/Kconfig"
565 source "src/vendorcode/*/Kconfig"
567 source "src/arch/*/Kconfig"
569 config CHIPSET_DEVICETREE
573 This symbol allows a chipset to provide a set of default settings in
574 a devicetree which are common to all mainboards. This may include
575 devices (including alias names), chip drivers, register settings,
576 and others. This path is relative to the src/ directory.
578 Example: "chipset.cb"
582 source "src/device/Kconfig"
584 menu "Generic Drivers"
585 source "src/drivers/*/Kconfig"
586 source "src/drivers/*/*/Kconfig"
587 source "src/drivers/*/*/*/Kconfig"
588 source "src/commonlib/storage/Kconfig"
593 source "src/security/Kconfig"
594 source "src/vendorcode/eltan/security/Kconfig"
598 source "src/acpi/Kconfig"
600 # This option is for the current boards/chipsets where SPI flash
601 # is not the boot device. Currently nearly all boards/chipsets assume
602 # SPI flash is the boot device.
603 config BOOT_DEVICE_NOT_SPI_FLASH
607 config BOOT_DEVICE_SPI_FLASH
609 default y if !BOOT_DEVICE_NOT_SPI_FLASH
612 config BOOT_DEVICE_MEMORY_MAPPED
614 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
617 Inform system if SPI is memory-mapped or not.
619 config BOOT_DEVICE_SUPPORTS_WRITES
623 Indicate that the platform has writable boot device
632 default 0x100000 if FLATTENED_DEVICE_TREE
637 default 0x1000 if ARCH_X86
644 source "src/console/Kconfig"
646 config HAVE_ACPI_RESUME
650 config DISABLE_ACPI_HIBERNATE
654 Removes S4 from the available sleepstates
656 config RESUME_PATH_SAME_AS_BOOT
658 default y if ARCH_X86
659 depends on HAVE_ACPI_RESUME
661 This option indicates that when a system resumes it takes the
662 same path as a regular boot. e.g. an x86 system runs from the
663 reset vector at 0xfffffff0 on both resume and warm/cold boot.
665 config NO_MONOTONIC_TIMER
668 config HAVE_MONOTONIC_TIMER
670 depends on !NO_MONOTONIC_TIMER
673 The board/chipset provides a monotonic timer.
675 config GENERIC_UDELAY
677 depends on HAVE_MONOTONIC_TIMER
678 default y if !ARCH_X86
680 The board/chipset uses a generic udelay function utilizing the
685 depends on HAVE_MONOTONIC_TIMER
687 Provide a timer queue for performing time-based callbacks.
689 config COOP_MULTITASKING
692 depends on ARCH_X86 && CPU_INFO_V2
694 Cooperative multitasking allows callbacks to be multiplexed on the
695 main thread. With this enabled it allows for multiple execution paths
696 to take place when they have udelay() calls within their code.
701 depends on COOP_MULTITASKING
703 How many execution threads to cooperatively multitask with.
705 config HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
708 Selected by mainboards which implement a mainboard-specific mechanism
709 to access the values for runtime-configurable options. For example, a
710 custom BMC interface or an EEPROM with an externally-imposed layout.
712 config HAVE_OPTION_TABLE
716 This variable specifies whether a given board has a cmos.layout
717 file containing NVRAM/CMOS bit definitions.
718 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
720 config CMOS_LAYOUT_FILE
722 default "src/mainboard/\$(MAINBOARDDIR)/cmos.layout"
723 depends on HAVE_OPTION_TABLE
725 config PCI_IO_CFG_EXT
734 config USE_WATCHDOG_ON_BOOT
742 Enable Unified Memory Architecture for graphics.
747 This variable specifies whether a given board has MP table support.
748 It is usually set in mainboard/*/Kconfig.
749 Whether or not the MP table is actually generated by coreboot
750 is configurable by the user via GENERATE_MP_TABLE.
752 config HAVE_PIRQ_TABLE
755 This variable specifies whether a given board has PIRQ table support.
756 It is usually set in mainboard/*/Kconfig.
757 Whether or not the PIRQ table is actually generated by coreboot
758 is configurable by the user via GENERATE_PIRQ_TABLE.
764 Build support for NHLT (non HD Audio) ACPI table generation.
766 #These Options are here to avoid "undefined" warnings.
767 #The actual selection and help texts are in the following menu.
771 config GENERATE_MP_TABLE
772 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
774 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
776 Generate an MP table (conforming to the Intel MultiProcessor
777 specification 1.4) for this board.
781 config GENERATE_PIRQ_TABLE
782 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
784 default HAVE_PIRQ_TABLE
786 Generate a PIRQ table for this board.
790 config GENERATE_SMBIOS_TABLES
792 bool "Generate SMBIOS tables"
795 Generate SMBIOS tables for this board.
799 config SMBIOS_TYPE41_PROVIDED_BY_DEVTREE
803 If enabled, only generate SMBIOS Type 41 entries for PCI devices in
804 the devicetree for which Type 41 information is provided, e.g. with
805 the `smbios_dev_info` devicetree syntax. This is useful to manually
806 assign specific instance IDs to onboard devices irrespective of the
807 device traversal order. It is assumed that instance IDs for devices
808 of the same class are unique.
809 When disabled, coreboot autogenerates SMBIOS Type 41 entries for all
810 appropriate PCI devices in the devicetree. Instance IDs are assigned
811 successive numbers from a monotonically increasing counter, with one
812 counter for each device class.
814 config SMBIOS_PROVIDED_BY_MOBO
818 config MAINBOARD_SERIAL_NUMBER
819 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
821 depends on GENERATE_SMBIOS_TABLES
824 The Serial Number to store in SMBIOS structures.
826 config MAINBOARD_VERSION
827 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
829 depends on GENERATE_SMBIOS_TABLES
832 The Version Number to store in SMBIOS structures.
834 config MAINBOARD_SMBIOS_MANUFACTURER
835 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
837 depends on GENERATE_SMBIOS_TABLES
838 default MAINBOARD_VENDOR
840 Override the default Manufacturer stored in SMBIOS structures.
842 config MAINBOARD_SMBIOS_PRODUCT_NAME
843 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
845 depends on GENERATE_SMBIOS_TABLES
846 default MAINBOARD_PART_NUMBER
848 Override the default Product name stored in SMBIOS structures.
850 config VPD_SMBIOS_VERSION
851 bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'"
853 depends on VPD && GENERATE_SMBIOS_TABLES
855 Selecting this option will read firmware_version from
856 VPD_RO and override SMBIOS type 0 version. One special
857 scenario of using this feature is to assign a BIOS version
858 to a coreboot image without the need to rebuild from source.
862 source "payloads/Kconfig"
866 comment "CPU Debug Settings"
867 source "src/cpu/*/Kconfig.debug_cpu"
869 comment "BLOB Debug Settings"
870 source "src/drivers/intel/fsp*/Kconfig.debug_blob"
872 comment "General Debug Settings"
874 # TODO: Better help text and detailed instructions.
876 bool "GDB debugging support"
878 depends on DRIVERS_UART
880 If enabled, you will be able to set breakpoints for gdb debugging.
881 See src/arch/x86/lib/c_start.S for details.
884 bool "Wait for a GDB connection in the ramstage"
888 If enabled, coreboot will wait for a GDB connection in the ramstage.
892 bool "Halt when hitting a BUG() or assertion error"
895 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
897 config HAVE_DEBUG_GPIO
901 bool "Output verbose GPIO debug messages"
902 depends on HAVE_DEBUG_GPIO
905 bool "Output verbose CBFS debug messages"
908 This option enables additional CBFS related debug messages.
910 config HAVE_DEBUG_RAM_SETUP
913 config DEBUG_RAM_SETUP
914 bool "Output verbose RAM init debug messages"
916 depends on HAVE_DEBUG_RAM_SETUP
918 This option enables additional RAM init related debug messages.
919 It is recommended to enable this when debugging issues on your
920 board which might be RAM init related.
922 Note: This option will increase the size of the coreboot image.
927 bool "Check PIRQ table consistency"
929 depends on GENERATE_PIRQ_TABLE
933 config HAVE_DEBUG_SMBUS
937 bool "Output verbose SMBus debug messages"
939 depends on HAVE_DEBUG_SMBUS
941 This option enables additional SMBus (and SPD) debug messages.
943 Note: This option will increase the size of the coreboot image.
948 bool "Output verbose SMI debug messages"
950 depends on HAVE_SMI_HANDLER
951 select SPI_FLASH_SMM if EM100PRO_SPI_CONSOLE || CONSOLE_SPI_FLASH
953 This option enables additional SMI related debug messages.
955 Note: This option will increase the size of the coreboot image.
959 config DEBUG_PERIODIC_SMI
960 bool "Trigger SMI periodically"
963 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
964 # printk(BIOS_DEBUG, ...) calls.
966 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
970 This option enables additional malloc related debug messages.
972 Note: This option will increase the size of the coreboot image.
976 # Only visible if DEBUG_SPEW (8) is set.
977 config DEBUG_RESOURCES
978 bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
981 This option enables additional PCI memory and IO debug messages.
982 Note: This option will increase the size of the coreboot image.
985 config DEBUG_CONSOLE_INIT
986 bool "Debug console initialisation code"
989 With this option printk()'s are attempted before console hardware
990 initialisation has been completed. Your mileage may vary.
992 Typically you will need to modify source in console_hw_init() such
993 that a working console appears before the one you want to debug.
997 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
998 # printk(BIOS_DEBUG, ...) calls.
999 config REALMODE_DEBUG
1000 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
1003 depends on PCI_OPTION_ROM_RUN_REALMODE
1005 This option enables additional x86emu related debug messages.
1007 Note: This option will increase the time to emulate a ROM.
1012 bool "Output verbose x86emu debug messages"
1014 depends on PCI_OPTION_ROM_RUN_YABEL
1016 This option enables additional x86emu related debug messages.
1018 Note: This option will increase the size of the coreboot image.
1022 config X86EMU_DEBUG_JMP
1023 bool "Trace JMP/RETF"
1025 depends on X86EMU_DEBUG
1027 Print information about JMP and RETF opcodes from x86emu.
1029 Note: This option will increase the size of the coreboot image.
1033 config X86EMU_DEBUG_TRACE
1034 bool "Trace all opcodes"
1036 depends on X86EMU_DEBUG
1038 Print _all_ opcodes that are executed by x86emu.
1040 WARNING: This will produce a LOT of output and take a long time.
1042 Note: This option will increase the size of the coreboot image.
1046 config X86EMU_DEBUG_PNP
1047 bool "Log Plug&Play accesses"
1049 depends on X86EMU_DEBUG
1051 Print Plug And Play accesses made by option ROMs.
1053 Note: This option will increase the size of the coreboot image.
1057 config X86EMU_DEBUG_DISK
1060 depends on X86EMU_DEBUG
1062 Print Disk I/O related messages.
1064 Note: This option will increase the size of the coreboot image.
1068 config X86EMU_DEBUG_PMM
1071 depends on X86EMU_DEBUG
1073 Print messages related to POST Memory Manager (PMM).
1075 Note: This option will increase the size of the coreboot image.
1080 config X86EMU_DEBUG_VBE
1081 bool "Debug VESA BIOS Extensions"
1083 depends on X86EMU_DEBUG
1085 Print messages related to VESA BIOS Extension (VBE) functions.
1087 Note: This option will increase the size of the coreboot image.
1091 config X86EMU_DEBUG_INT10
1092 bool "Redirect INT10 output to console"
1094 depends on X86EMU_DEBUG
1096 Let INT10 (i.e. character output) calls print messages to debug output.
1098 Note: This option will increase the size of the coreboot image.
1102 config X86EMU_DEBUG_INTERRUPTS
1103 bool "Log intXX calls"
1105 depends on X86EMU_DEBUG
1107 Print messages related to interrupt handling.
1109 Note: This option will increase the size of the coreboot image.
1113 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1114 bool "Log special memory accesses"
1116 depends on X86EMU_DEBUG
1118 Print messages related to accesses to certain areas of the virtual
1119 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1121 Note: This option will increase the size of the coreboot image.
1125 config X86EMU_DEBUG_MEM
1126 bool "Log all memory accesses"
1128 depends on X86EMU_DEBUG
1130 Print memory accesses made by option ROM.
1131 Note: This also includes accesses to fetch instructions.
1133 Note: This option will increase the size of the coreboot image.
1137 config X86EMU_DEBUG_IO
1138 bool "Log IO accesses"
1140 depends on X86EMU_DEBUG
1142 Print I/O accesses made by option ROM.
1144 Note: This option will increase the size of the coreboot image.
1148 config X86EMU_DEBUG_TIMINGS
1149 bool "Output timing information"
1151 depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
1153 Print timing information needed by i915tool.
1157 config DEBUG_SPI_FLASH
1158 bool "Output verbose SPI flash debug messages"
1160 depends on SPI_FLASH
1162 This option enables additional SPI flash related debug messages.
1165 bool "Output verbose IPMI debug messages"
1169 This option enables additional IPMI related debug messages.
1171 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1172 # Only visible with the right southbridge and loglevel.
1173 config DEBUG_INTEL_ME
1174 bool "Verbose logging for Intel Management Engine"
1177 Enable verbose logging for Intel Management Engine driver that
1178 is present on Intel 6-series chipsets.
1182 bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
1185 This option enables additional function entry and exit debug messages
1186 for select functions.
1187 Note: This option will increase the size of the coreboot image.
1190 config DEBUG_COVERAGE
1191 bool "Debug code coverage"
1195 If enabled, the code coverage hooks in coreboot will output some
1196 information about the coverage data that is dumped.
1198 config DEBUG_BOOT_STATE
1199 bool "Debug boot state machine"
1202 Control debugging of the boot state machine. When selected displays
1203 the state boundaries in ramstage.
1205 config DEBUG_ADA_CODE
1206 bool "Compile debug code in Ada sources"
1209 Add the compiler switch `-gnata` to compile code guarded by
1212 config HAVE_EM100_SUPPORT
1213 bool "Platform can support the Dediprog EM100 SPI emulator"
1215 This is enabled by platforms which can support using the EM100.
1218 bool "Configure image for EM100 usage"
1219 depends on HAVE_EM100_SUPPORT
1221 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1222 over USB. However it only supports a maximum SPI clock of 20MHz and
1223 single data output. Enable this option to use a 20MHz SPI clock and
1224 disable "Dual Output Fast Read" Support.
1226 On AMD platforms this changes the SPI speed at run-time if the
1227 mainboard code supports this. On supported Intel platforms this works
1228 by changing the settings in the descriptor.bin file.
1232 ###############################################################################
1233 # Set variables with no prompt - these can be set anywhere, and putting at
1234 # the end of this file gives the most flexibility.
1236 source "src/lib/Kconfig"
1238 config WARNINGS_ARE_ERRORS
1242 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1243 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1244 # mutually exclusive. One of these options must be selected in the
1245 # mainboard Kconfig if the chipset supports enabling and disabling of
1246 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1247 # in mainboard/Kconfig to know if the button should be enabled or not.
1249 config POWER_BUTTON_DEFAULT_ENABLE
1252 Select when the board has a power button which can optionally be
1253 disabled by the user.
1255 config POWER_BUTTON_DEFAULT_DISABLE
1258 Select when the board has a power button which can optionally be
1259 enabled by the user, e.g. when the board ships with a jumper over
1260 the power switch contacts.
1262 config POWER_BUTTON_FORCE_ENABLE
1265 Select when the board requires that the power button is always
1268 config POWER_BUTTON_FORCE_DISABLE
1271 Select when the board requires that the power button is always
1272 disabled, e.g. when it has been hardwired to ground.
1274 config POWER_BUTTON_IS_OPTIONAL
1276 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1277 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1279 Internal option that controls ENABLE_POWER_BUTTON visibility.
1285 Internal option that controls whether we compile in register scripts.
1287 config MAX_REBOOT_CNT
1291 Internal option that sets the maximum number of bootblock executions allowed
1292 with the normal image enabled before assuming the normal image is defective
1293 and switching to the fallback image.
1295 config UNCOMPRESSED_RAMSTAGE
1298 config NO_XIP_EARLY_STAGES
1300 default n if ARCH_X86
1303 Identify if early stages are eXecute-In-Place(XIP).
1305 config EARLY_CBMEM_LIST
1309 Enable display of CBMEM during romstage and postcar.
1311 config RELOCATABLE_MODULES
1314 If RELOCATABLE_MODULES is selected then support is enabled for
1315 building relocatable modules in the RAM stage. Those modules can be
1316 loaded anywhere and all the relocations are handled automatically.
1318 config GENERIC_GPIO_LIB
1321 If enabled, compile the generic GPIO library. A "generic" GPIO
1322 implies configurability usually found on SoCs, particularly the
1323 ability to control internal pull resistors.
1325 config BOOTBLOCK_CUSTOM
1326 # To be selected by arch, SoC or mainboard if it does not want use the normal
1327 # src/lib/bootblock.c#main() C entry point.
1330 config MEMLAYOUT_LD_FILE
1332 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld"
1334 This variable allows SoC/mainboard to supply in a custom linker file
1335 if required. This determines the linker file used for all the stages
1336 (bootblock, romstage, verstage, ramstage, postcar) in
1337 src/arch/${ARCH}/Makefile.inc.
1339 ###############################################################################
1340 # Set default values for symbols created before mainboards. This allows the
1341 # option to be displayed in the general menu, but the default to be loaded in
1342 # the mainboard if desired.
1343 config COMPRESS_RAMSTAGE
1344 default y if !UNCOMPRESSED_RAMSTAGE
1346 config COMPRESS_PRERAM_STAGES
1347 depends on !ARCH_X86
1350 config INCLUDE_CONFIG_FILE
1353 config BOOTSPLASH_FILE
1354 depends on BOOTSPLASH_IMAGE
1355 default "bootsplash.jpg"
1360 config HAVE_BOOTBLOCK
1364 config HAVE_VERSTAGE
1366 depends on VBOOT_SEPARATE_VERSTAGE
1369 config HAVE_ROMSTAGE
1373 config HAVE_RAMSTAGE
1375 default n if RAMPAYLOAD