src/soc/intel/cannonlake/acpi/southbridge.asl

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /* PCI IRQ assignment */
   4 #include "pci_irqs.asl"
   5
   6 /* PCR access */
   7 #include <soc/intel/common/acpi/pcr.asl>
   8
   9 /* eMMC, SD Card */
  10 #include "scs.asl"
  11
  12 /* GPIO controller */
  13 #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
  14 #include "gpio_cnp_h.asl"
  15 #else
  16 #include "gpio.asl"
  17 #endif
  18
  19 /* GFX 00:02.0 */
  20 #include "gfx.asl"
  21
  22 /* LPC 0:1f.0 */
  23 #include <soc/intel/common/block/acpi/acpi/lpc.asl>
  24
  25 /* PCH HDA */
  26 #include "pch_hda.asl"
  27
  28 /* PCIE Ports */
  29 #include "pcie.asl"
  30
  31 /* Serial IO */
  32 #include "serialio.asl"
  33
  34 /* SMBus 0:1f.4 */
  35 #include <soc/intel/common/block/acpi/acpi/smbus.asl>
  36
  37 /* ISH 0:13.0 */
  38 #include "ish.asl"
  39
  40 /* USB XHCI 0:14.0 */
  41 #include "xhci.asl"
  42
  43 /* PCI _OSC */
  44 #include <soc/intel/common/acpi/pci_osc.asl>
  45
  46 /* GbE 0:1f.6 */
  47 #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
  48
  49 /* PMC Core */
  50 #include <soc/intel/common/block/acpi/acpi/pmc.asl>